公开(公告)号：US20240006284A1

公开(公告)日：2024-01-04

申请号：US17855298

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Benjamin Duong ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/16 ,  H01L23/49894 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L23/5386

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

公开(公告)号：US11855125B2

公开(公告)日：2023-12-26

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Brandon C. Marin ,  Jeremy Ecton ,  Hiroki Tanaka ,  Frank Truong

IPC: H01L21/48 ,  H01G4/008 ,  H01G4/28 ,  H01G4/12 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/28 ,  H01L21/4846

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US11780210B2

公开(公告)日：2023-10-10

申请号：US16574252

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Gang Duan ,  Srinivas Pietambaram ,  Patrick Quach ,  Dilan Seneviratne

IPC: H01L21/00 ,  B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC classification number: B32B17/10192 ,  B32B15/20 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/02379

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20220404553A1

公开(公告)日：2022-12-22

申请号：US17354446

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Ankur Agrawal ,  Benjamin Duong ,  Ravindranath Mahajan ,  Debendra Mallik ,  Srinivas Pietambaram

IPC: G02B6/26

Abstract: An integrated circuit package may be formed comprising a first integrated circuit assembly, a second integrated circuit assembly, and a means to transfer optical signals therebetween. This optical signal transfer may be facilitated with a first lens or a first micro-lens array adjacent at least one waveguide of the first integrated circuit assembly and a second lens or second micro-lens array adjacent at least one waveguide of the second integrated circuit assembly, wherein the optical signals are transmitted across a gap between the first lens/micro-lens array and the second lens/micro-lens array. In further embodiments, the optical signal transfer assembly may comprise at least one photonic bridge between at least one waveguide of the first integrated circuit assembly and at least one waveguide of the second integrated circuit assembly.

公开(公告)号：US11264307B2

公开(公告)日：2022-03-01

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Hiroki Tanaka ,  Robert A. May ,  Kristof Darmawikarta ,  Changhua Liu ,  Chung Kwang Tan ,  Srinivas Pietambaram ,  Sri Ranga Sai Boyapati

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20210280463A1

公开(公告)日：2021-09-09

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US20200211952A1

公开(公告)日：2020-07-02

申请号：US16814215

申请日：2020-03-10

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US10204855B2

公开(公告)日：2019-02-12

申请号：US14653033

申请日：2014-07-11

Applicant: Intel Corporation

Inventor： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC: H01L23/00 ,  H01L23/498 ,  B23B5/16 ,  B32B27/08 ,  B32B27/28 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H05K1/02

Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

公开(公告)号：US10080290B2

公开(公告)日：2018-09-18

申请号：US14943234

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Srinivas Pietambaram ,  Rahul N. Manepalli

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/184 ,  H01L2224/04105 ,  H01L2924/18162 ,  H05K1/0283 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/007 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0191 ,  H05K2203/1469

Abstract: An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

公开(公告)号：US12255147B2

公开(公告)日：2025-03-18

申请号：US17243784

申请日：2021-04-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.