公开(公告)号：US20160316567A1

公开(公告)日：2016-10-27

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H05K3/32 ,  H05K1/11 ,  H05K1/02 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

Abstract translation: 半导体模块包括电路板和埋入电路板中的功率半导体芯片。 功率半导体芯片具有第一负载电极。 半导体模块还包括电连接到第一负载电极的电源端子连接器。 嵌入式功率半导体芯片横向定位在电源端子连接器的覆盖区域内。

公开(公告)号：US20250118614A1

公开(公告)日：2025-04-10

申请号：US18480620

申请日：2023-10-04

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Michael Fügl

IPC: H01L23/34 ,  H01L23/053 ,  H01L23/31 ,  H01L25/065

Abstract: A molded package includes: a mold compound; a first power semiconductor die encapsulated by the mold compound; and a first temperature sense cavity formed in a surface of the mold compound. The molded package is devoid of temperature sense terminals. The first temperature sense cavity is dimensioned to receive a temperature sensor and/or a combined area of each sidewall and a bottom of the first temperature sense cavity is greater than an area of an opening in the surface of the mold compound that delineates the first temperature sense cavity. A corresponding power module and a power electronics assembly that includes the molded package or the power module are also described.

公开(公告)号：US12218098B2

公开(公告)日：2025-02-04

申请号：US17722929

申请日：2022-04-18

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/498

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

公开(公告)号：US20240395676A1

公开(公告)日：2024-11-28

申请号：US18670000

申请日：2024-05-21

Applicant: Infineon Technologies AG

Inventor： Marcus Böhm ,  Bernd Richard Schmölzer ,  Lisa Marie Holzmann ,  Thorsten Scharf

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.

公开(公告)号：US12027481B2

公开(公告)日：2024-07-02

申请号：US18103204

申请日：2023-01-30

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  H05K1/18 ,  H05K3/00

CPC classification number: H01L24/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L25/04 ,  H05K1/188 ,  H05K3/007 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H05K2203/0152 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US11915999B2

公开(公告)日：2024-02-27

申请号：US18103865

申请日：2023-01-31

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L25/065 ,  H01L25/075 ,  H01L25/04 ,  H02P27/06

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4012 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/043 ,  H01L25/0655 ,  H01L25/0756 ,  H01L2924/181 ,  H02P27/06 ,  H02P2201/03

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

公开(公告)号：US20230187326A1

公开(公告)日：2023-06-15

申请号：US18103865

申请日：2023-01-31

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49568 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/3107 ,  H01L25/0655 ,  H02P2201/03 ,  H02P27/06

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

公开(公告)号：US11600558B2

公开(公告)日：2023-03-07

申请号：US16845304

申请日：2020-04-10

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H02P27/06

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

公开(公告)号：US20220108974A1

公开(公告)日：2022-04-07

申请号：US17491647

申请日：2021-10-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Alexander Heinrich ,  Steffen Jordan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

公开(公告)号：US20210035879A1

公开(公告)日：2021-02-04

申请号：US16943054

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Thorsten Scharf

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.