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公开(公告)号:US11854787B2
公开(公告)日:2023-12-26
申请号:US17735006
申请日:2022-05-02
Applicant: Intel Corporation
Inventor: Richard E. Schenker , Robert L. Bristol , Kevin L. Lin , Florian Gstrein , James M. Blackwell , Marie Krysak , Manish Chandhok , Paul A. Nyhus , Charles H. Wallace , Curtis W. Ward , Swaminathan Sivakumar , Elliot N. Tan
IPC: H01L23/528 , H01L23/522 , H01L23/532 , H01L27/088 , H01L29/78
CPC classification number: H01L23/528 , H01L23/5226 , H01L23/5329 , H01L23/53238 , H01L27/0886 , H01L29/7848
Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
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公开(公告)号:US10811351B2
公开(公告)日:2020-10-20
申请号:US16316528
申请日:2016-09-26
Applicant: Intel Corporation
Inventor: Elliot N. Tan
IPC: H01L23/522 , H01L21/768 , H01L23/498
Abstract: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
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公开(公告)号:US09659860B2
公开(公告)日:2017-05-23
申请号:US14905269
申请日:2013-08-21
Applicant: Intel Corporation
Inventor: Richard E. Schenker , Elliot N. Tan
IPC: H01L23/532 , H01L21/02 , H01L21/033 , H01L21/311 , H01L23/528 , H01L23/522 , H01L21/768
CPC classification number: H01L23/5226 , H01L21/02115 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
Abstract: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.
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公开(公告)号:US12249541B2
公开(公告)日:2025-03-11
申请号:US18096351
申请日:2023-01-12
Applicant: Intel Corporation
Inventor: Leonard P. Guler , Chul-Hyun Lim , Paul A. Nyhus , Elliot N. Tan , Charles H. Wallace
IPC: H01L21/768 , H01L21/311 , H01L29/417 , H01L29/423
Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.
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公开(公告)号:US11594448B2
公开(公告)日:2023-02-28
申请号:US16435259
申请日:2019-06-07
Applicant: Intel Corporation
Inventor: Leonard P. Guler , Chul-Hyun Lim , Paul A. Nyhus , Elliot N. Tan , Charles H. Wallace
IPC: H01L21/768 , H01L21/311 , H01L29/423 , H01L29/417
Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.
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公开(公告)号:US20220415897A1
公开(公告)日:2022-12-29
申请号:US17358954
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Juan G. Alzate-Vinasco , Travis W. LaJoie , Elliot N. Tan , Kimberly Pierce , Shem Ogadhoh , Abhishek A. Sharma , Bernhard Sell , Pei-Hua Wang , Chieh-Jen Ku
IPC: H01L27/108 , H01L29/786 , H01L29/66
Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.
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17.
公开(公告)号:US10600678B2
公开(公告)日:2020-03-24
申请号:US16246373
申请日:2019-01-11
Applicant: Intel Corporation
Inventor: Charles H. Wallace , Elliot N. Tan , Paul A. Nyhus , Swaminathan Sivakumar
IPC: H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
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公开(公告)号:US11950407B2
公开(公告)日:2024-04-02
申请号:US16828507
申请日:2020-03-24
Applicant: Intel Corporation
Inventor: Juan G. Alzate Vinasco , Travis W. Lajoie , Abhishek A. Sharma , Kimberly L Pierce , Elliot N. Tan , Yu-Jin Chen , Van H. Le , Pei-Hua Wang , Bernhard Sell
IPC: H10B12/00 , H01L23/522 , H01L23/528 , H01L49/02
CPC classification number: H10B12/315 , H01L23/5226 , H01L23/528 , H01L28/91 , H10B12/0335 , H10B12/05 , H10B12/318 , H10B12/482 , H10B12/485
Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
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19.
公开(公告)号:US20230290825A1
公开(公告)日:2023-09-14
申请号:US17693136
申请日:2022-03-11
Applicant: Intel Corporation
Inventor: Leonard P. Guler , Sean Pursel , Raghuram Gandikota , Sikandar Abbas , Tsuan-Chung Chang , Mauro J. Kobrinsky , Tahir Ghani , Elliot N. Tan
IPC: H01L29/06 , H01L29/423 , H01L29/786 , H01L29/417 , H01L29/66 , H01L27/088
CPC classification number: H01L29/0673 , H01L29/42392 , H01L29/78618 , H01L29/78696 , H01L29/41733 , H01L29/66742 , H01L27/0886
Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.
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20.
公开(公告)号:US10211088B2
公开(公告)日:2019-02-19
申请号:US15743616
申请日:2015-09-10
Applicant: INTEL CORPORATION , Charles H. Wallace , Swaminathan Sivakumar
Inventor: Charles H. Wallace , Elliot N. Tan , Paul A. Nyhus , Swaminathan Sivakumar
IPC: H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
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