公开(公告)号：US09611372B2

公开(公告)日：2017-04-04

申请号：US15047866

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Yonghao Xiu ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Arjun Krishnan

IPC: H01L21/50 ,  C08K3/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: C08K3/013 ,  H01L21/563 ,  H01L23/295 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0493 ,  H01L2924/053 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/186 ,  H01L2924/0665 ,  H01L2924/05032 ,  H01L2924/014

Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.

公开(公告)号：US20160343591A1

公开(公告)日：2016-11-24

申请号：US15225678

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen-Givoni ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160240395A1

公开(公告)日：2016-08-18

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L24/13 ,  H01L2224/16225 ,  H01L2224/29647 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括用硫醇粘合促进剂，唑偶合剂，表面改性填料和基于过氧化物的交联聚合物化学物质之一改性底部填充材料，以便利用本文的实施方案极大地增强包装结构中的粘合性。

公开(公告)号：US20240222321A1

公开(公告)日：2024-07-04

申请号：US18148533

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US09631065B2

公开(公告)日：2017-04-25

申请号：US13795021

申请日：2013-03-12

Applicant: INTEL CORPORATION

Inventor： Anna M. Prakash ,  James C. Matayabas ,  Arjun Krishnan ,  Nisha Ananthakrishnan

IPC: H01L21/56 ,  H01L23/29 ,  C08K5/00 ,  H01L21/78 ,  B23K26/18 ,  B23K26/364

CPC classification number: C08K5/005 ,  B23K26/18 ,  B23K26/364 ,  H01L21/563 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.

公开(公告)号：US09458283B2

公开(公告)日：2016-10-04

申请号：US14746750

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Dingying Xu ,  Nisha Ananthakrishnan ,  Hong Dong ,  Rahul N. Manepalli ,  Nachiket R. Raravikar ,  Gregory S. Constable

IPC: C08G77/04 ,  C08L63/00 ,  B32B27/38 ,  C08G59/02 ,  C08L23/08 ,  H01L21/56 ,  H01L23/29 ,  C08G59/32 ,  C08G59/38 ,  C07F7/08 ,  H01L23/00

CPC classification number: C08G59/02 ,  C07F7/0838 ,  C08G59/3254 ,  C08G59/38 ,  C08L23/0884 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3512 ,  Y10T428/31515 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

公开(公告)号：US20150166804A1

公开(公告)日：2015-06-18

申请号：US14556994

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Randall D. Lowe, JR. ,  Suriyakala Suriya Ramalingam ,  Nisha Ananthakrishnan ,  James C. Matayabas, JR. ,  Arjun Krishnan ,  Hitesh Arora

IPC: C09D11/107 ,  H01L21/56 ,  H01L23/544 ,  H01L23/29

CPC classification number: H01L21/56 ,  C09D11/101 ,  C09D11/20 ,  H01L23/296 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Abstract translation: 本文公开了在光引发剂存在下使用UV诱导的聚合方法将聚丙烯酸酯聚合物共价且不可分割地锚定到氧化物表面的方法。 通过该方法制备的方法和组合物可用作用于微电子封装的不可擦除的标记材料，以及用作焊料和密封剂屏障以防止液体在微电子封装的氧化物表面上的过度扩散。 在通过连接剂与丙烯酸酯反应性基团键合的作为第一结构域的氧化物反应性甲硅烷基的粘合促进剂的印刷和UV固化过程中，聚丙烯酸酯聚合物共价连接到氧化物表面。

公开(公告)号：US20240222326A1

公开(公告)日：2024-07-04

申请号：US18148528

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00 ,  H10B12/00 ,  H10B80/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12 ,  H10B12/37 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US11776821B2

公开(公告)日：2023-10-03

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L21/563 ,  H01L21/67126 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/564 ,  H05K2201/09045

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

公开(公告)号：US11282717B2

公开(公告)日：2022-03-22

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.