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公开(公告)号：US20190146714A1
公开(公告)日：2019-05-16
申请号：US16234655
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Niranjan Cooray , Prasoonkumar Surti , John Feit
Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.
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公开(公告)号：US11729403B2
公开(公告)日：2023-08-15
申请号：US16647998
申请日：2017-12-05
Applicant: INTEL CORPORATION
Inventor： James Holland , Hiu-Fai Chan , Fangwen Fu , Qian Xu , Sang-Hee Lee , Vidhya Krishnan
IPC: H04N11/02 , H04N19/182 , H04N19/423
CPC classification number: H04N19/182 , H04N19/423
Abstract: A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.
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公开(公告)号：US20220222185A1
公开(公告)日：2022-07-14
申请号：US17712109
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Siddhartha Chhabra , David Puffer , Ankur Shah , Daniel Nemiroff , Utkarsh Y. Kakaiya
Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.
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公开(公告)号：US20220004635A1
公开(公告)日：2022-01-06
申请号：US17480601
申请日：2021-09-21
Applicant: Intel Corporation
Inventor： Daniel Nemiroff , Vidhya Krishnan , Bryan R. White
Abstract: An apparatus is disclosed. The apparatus comprises a trusted device including a first integrated circuit (IC) die comprising a first plurality of hardware devices and a second IC die comprising a second plurality of hardware devices and cryptographic processor to operate as a root of trust to manage an input/output (I/O) functional state of each of the hardware devices.
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公开(公告)号：US10915608B2
公开(公告)日：2021-02-09
申请号：US16126060
申请日：2018-09-10
Applicant: Intel Corporation
Inventor： Balaji Vembu , Vidhya Krishnan , Sandeep Sodhi , Sreekanth Mavila , Altug Koker , Aditya Navale , Scott Janus , Changliang Wang
IPC: H04L9/00 , G06F21/12 , G06T15/00 , H04N21/254 , G06F9/48 , H04L9/08 , G06F21/60 , G06T1/20 , G06T1/60
Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.
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Patent Agency Ranking
公开(公告)号：US10802970B1
公开(公告)日：2020-10-13
申请号：US16366266
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Niranjan L. Cooray , Altug Koker , Vidhya Krishnan , Ronald W. Silvas , John H. Feit , Prasoonkumar Surti , Joydeep Ray , Abhishek R. Appu
IPC: G06F12/0837 , G06F9/38 , G06F16/907 , H04L9/06 , G06F12/0811
Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.
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公开(公告)号：US20190139184A1
公开(公告)日：2019-05-09
申请号：US16235641
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Atthar Mohammed , Hiu-Fai Chan , Hyeong-Seok Ha , Jong Dae Oh , Karthik Nagasubramanian , Ping Liu , Samuel Wong , Satya Yedidi , Sumit Mohan , Vidhya Krishnan , Pavan Kumar Saranu , Ashokanand N
IPC: G06T1/20 , H04N19/42 , H04N19/30 , G06F9/38 , H04N19/172
Abstract: Methods, apparatuses and systems may provide for technology that processes portions of video frames in different hardware pipes. More particularly, implementations relate to technology that provides splitting of a frame into columns or rows and processing each of these in different hardware pipes and managing the dependency in hardware. Such operations may achieve this support while at the same time providing enough flexibility to use these pipes independently when the higher performance is not required.
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公开(公告)号：US11816040B2
公开(公告)日：2023-11-14
申请号：US17712109
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Siddhartha Chhabra , David Puffer , Ankur Shah , Daniel Nemiroff , Utkarsh Y. Kakaiya
CPC classification number: G06F12/1433 , G06F11/1004 , G06F12/0292 , G06F12/1408 , G06F12/1466 , G06F12/1483
Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.
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公开(公告)号：US20230306551A1
公开(公告)日：2023-09-28
申请号：US17702301
申请日：2022-03-23
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Niranjan Cooray , David Puffer , Ronald Silvas , Durgaprasad Bilagi , Aditya Navale
CPC classification number: G06T1/20 , G06F12/0223 , G06T1/60 , G06T9/00 , G06F2212/401
Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.
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公开(公告)号：US20230298125A1
公开(公告)日：2023-09-21
申请号：US17827444
申请日：2022-05-27
Applicant: Intel Corporation
Inventor： Hema Chand Nalluri , Jeffery S. Boles , David Cowperthwaite , Aditya Navale , Prasoonkumar Surti , Arthur Hunter , Vasanth Ranganathan , Joydeep Ray , David Puffer , Ankur Shah , Vidhya Krishnan , Kritika Bala , Aravindh Anantaraman , Michael Apodaca , Kenneth Daxer
CPC classification number: G06T1/20 , G06T15/005 , G06T1/60 , G06F9/4881 , G06F9/5061 , G06F9/505 , G06T2200/16
Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.
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