公开(公告)号：US20170170031A1

公开(公告)日：2017-06-15

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US10790222B2

公开(公告)日：2020-09-29

申请号：US16361116

申请日：2019-03-21

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US09502372B1

公开(公告)日：2016-11-22

申请号：US14701049

申请日：2015-04-30

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US10354945B2

公开(公告)日：2019-07-16

申请号：US15660718

申请日：2017-07-26

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Min Tao ,  Javier A. Delacruz ,  Hoki Kim ,  Akash Agrawal

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L25/10 ,  H01L23/498

Abstract: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

公开(公告)号：US09824974B2

公开(公告)日：2017-11-21

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Hong Shen ,  Arkalgud R. Sitaram ,  Liang Wang ,  Akash Agrawal ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

公开(公告)号：US09728524B1

公开(公告)日：2017-08-08

申请号：US15198615

申请日：2016-06-30

Applicant: Invensas Corporation

Inventor： Min Tao ,  Zhuowen Sun ,  Hoki Kim ,  Wael Zohni ,  Akash Agrawal

IPC: H01L23/49 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01L25/105 ,  H01L23/49805 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589 ,  H05K1/11 ,  H05K1/181 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.

公开(公告)号：US20170069591A1

公开(公告)日：2017-03-09

申请号：US15357553

申请日：2016-11-21

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US09548273B2

公开(公告)日：2017-01-17

申请号：US14704714

申请日：2015-05-05

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Hong Shen ,  Arkalgud R. Sitaram ,  Liang Wang ,  Akash Agrawal ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract translation: 模具（110）和/或未开封的晶片和/或多芯片模块（MCM）被附接在插入器（120）或一些其它结构（例如另一集成电路）的顶部上并被密封剂（160）覆盖。 然后插入器从下面变薄。 在封装之前，在封装周围的插入件周围形成比密封剂更刚性的层（410），以通过机械工艺（例如CMP）来减小或消除插入件在裸片间的凹陷。 还提供其他功能。

公开(公告)号：US09543277B1

公开(公告)日：2017-01-10

申请号：US14830973

申请日：2015-08-20

Applicant: Invensas Corporation

Inventor： Bongsub Lee ,  Tu Tam Vu ,  Rajesh Katkar ,  Laura Wills Mirkarimi ,  Akash Agrawal ,  Kyong-Mo Bang ,  Gabriel Z. Guevara ,  Xuan Li ,  Long Huynh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/06 ,  H01L24/43 ,  H01L24/46 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/18165 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05599

Abstract: A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.

Abstract translation: 提供了一种扇出式微电子封装，其中，接合线将微电子元件（例如，可能在其上具有附加迹线的半导体芯片）上的接合焊盘电耦合，并且电介质元件的邻近边缘表面的电介质元件的扇出区域处的触点 芯片。 接合线将微电子元件与扇出区域机械地分离，这可以使得由于差分热膨胀的影响而导致电互连不容易产生可靠性问题，例如由初始封装制造，接合操作或热循环期间的温度漂移引起的 。 此外，由接合线提供的机械解耦也可以补救其他机械问题，例如冲击和包装元件的可能的分层。