公开(公告)号：US20200082246A1

公开(公告)日：2020-03-12

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R. Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06N3/04 ,  G06N3/08 ,  G06F9/54 ,  G06F9/445

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

公开(公告)号：US20190325092A1

公开(公告)日：2019-10-24

申请号：US15960833

申请日：2018-04-24

Applicant: NVIDIA Corp.

Inventor： Mark Ren ,  Brucek Khailany

IPC: G06F17/50 ,  G06N3/04 ,  G06N3/08

Abstract: A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.