公开(公告)号：US12099407B2

公开(公告)日：2024-09-24

申请号：US17737374

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Kumar Sastry Hari ,  Brian Matthew Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

CPC classification number: G06F11/102 ,  G06F9/30029 ,  G06F9/30116 ,  G06F11/0772 ,  G06F11/1044

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20220269558A1

公开(公告)日：2022-08-25

申请号：US17737374

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Kumar Sastry Hari ,  Brian Matthew Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20200082246A1

公开(公告)日：2020-03-12

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R. Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06N3/04 ,  G06N3/08 ,  G06F9/54 ,  G06F9/445

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

公开(公告)号：US20250132892A1

公开(公告)日：2025-04-24

申请号：US18492126

申请日：2023-10-23

Applicant: NVIDIA Corp.

Inventor： Brian Matthew Zimmer

IPC: H04L7/00 ,  H04L7/033

Abstract: Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.

公开(公告)号：US11769040B2

公开(公告)日：2023-09-26

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06F7/02 ,  G06N3/049 ,  G06F9/445 ,  G06F9/54 ,  G06N3/082

CPC classification number: G06N3/049 ,  G06F9/44505 ,  G06F9/544 ,  G06N3/082

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.