公开(公告)号：US11977386B2

公开(公告)日：2024-05-07

申请号：US18057079

申请日：2022-11-18

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler ,  Alejandro Troccoli

IPC: G05D1/00 ,  B60W60/00 ,  G01S13/931 ,  G05B13/02

CPC classification number: G05D1/0214 ,  B60W60/0015 ,  G01S13/931 ,  G05B13/027 ,  G05D1/0088 ,  B60W2554/4046 ,  B60W2710/20 ,  B60W2720/106 ,  B60W2720/125

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

公开(公告)号：US11270197B2

公开(公告)日：2022-03-08

申请号：US16672918

申请日：2019-11-04

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Miaorong Wang ,  Daniel Smith ,  William James Dally ,  Joel Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06F17/16 ,  G06N3/063 ,  G06F9/38 ,  G06N3/08

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.

公开(公告)号：US20220269558A1

公开(公告)日：2022-08-25

申请号：US17737374

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Kumar Sastry Hari ,  Brian Matthew Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20210389769A1

公开(公告)日：2021-12-16

申请号：US16898308

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler ,  Alejandro Troccoli

IPC: G05D1/02 ,  G01S13/931 ,  G05D1/00 ,  B60W60/00 ,  G05B13/02

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

公开(公告)号：US20210387643A1

公开(公告)日：2021-12-16

申请号：US16898379

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler

IPC: B60W60/00 ,  B60W30/09 ,  B60W30/095

Abstract: Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.

公开(公告)号：US10817289B2

公开(公告)日：2020-10-27

申请号：US16150410

申请日：2018-10-03

Applicant: NVIDIA Corp.

Inventor： Siva Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler ,  Abdulrahman Mahmoud

IPC: G06F11/14 ,  G06F9/30 ,  G06F11/10

Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.

公开(公告)号：US11550325B2

公开(公告)日：2023-01-10

申请号：US16898308

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler ,  Alejandro Troccoli

IPC: G05D1/02 ,  G01S13/931 ,  G05D1/00 ,  B60W60/00 ,  G05B13/02

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

公开(公告)号：US20210004235A1

公开(公告)日：2021-01-07

申请号：US17024683

申请日：2020-09-17

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F11/14 ,  G06F11/07

Abstract: A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.

公开(公告)号：US20200082246A1

公开(公告)日：2020-03-12

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R. Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06N3/04 ,  G06N3/08 ,  G06F9/54 ,  G06F9/445

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

公开(公告)号：US11769040B2

公开(公告)日：2023-09-26

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06F7/02 ,  G06N3/049 ,  G06F9/445 ,  G06F9/54 ,  G06N3/082

CPC classification number: G06N3/049 ,  G06F9/44505 ,  G06F9/544 ,  G06N3/082

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.