公开(公告)号：US10409525B2

公开(公告)日：2019-09-10

申请号：US14860722

申请日：2015-09-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory management method for a rewritable non-volatile memory module is provided. The method includes: selecting at least one first physical erasing unit from at least part of physical erasing units according to a first parameter. The method further includes: selecting a second physical erasing unit from the at least one first physical erasing unit according to a second parameter, wherein the second parameter is different from the first parameter; and copying at least part of data stored in the second physical erasing unit to a third physical erasing unit.

公开(公告)号：US20170262197A1

公开(公告)日：2017-09-14

申请号：US15145814

申请日：2016-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G11C16/3427 ,  G11C16/3431

Abstract: A memory managing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: setting a read-disturb threshold for each of a plurality of physical erasing units; adjusting the read-disturb threshold of a first physical erasing unit according to state information of a rewritable non-volatile memory module; and performing a read-disturb prevention operation according to the read-disturb threshold of the first physical erasing unit.

公开(公告)号：US09665481B2

公开(公告)日：2017-05-30

申请号：US14824092

申请日：2015-08-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F13/00 ,  G06F12/02 ,  G11C16/16 ,  G11C16/00 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7211 ,  G11C16/00 ,  G11C16/16 ,  G11C16/349 ,  G11C16/3495

Abstract: A wear leveling method for a rewritable non-volatile memory module is provided. The method includes: recording a timestamp for each of physical erasing units storing valid data according to a programming sequence of the physical erasing units storing valid data among the physical erasing units, and recording an erase count for each of physical erasing units. The method also includes: selecting a first physical erasing unit from the physical erasing units storing valid data according to the timestamps, selecting a second physical erasing unit from physical erasing units not storing valid data among the physical erasing units according to the erase counts, and writing valid data of the first physical erasing unit into the second physical erasing unit, and marking the first physical erasing unit as a physical erasing unit not storing valid data.

公开(公告)号：US20170139642A1

公开(公告)日：2017-05-18

申请号：US15007222

申请日：2016-01-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0656 ,  G06F3/0617 ,  G06F3/0631 ,  G06F3/0679 ,  G06F12/0804 ,  G06F2212/222 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The method includes allocating a first zone and a second zone in the buffer memory for temporarily storing a plurality of logical address-physical address mapping tables and performing a restore operation on the first zone. The method also includes receiving a write command, wherein a logical address-physical address table to which a logical address indicated by the write command belongs has been temporarily stored in the first zone. The method further includes copying the logical address-physical address table into the second zone, and updating the logical address-physical address table in the second zone.

公开(公告)号：US09639475B2

公开(公告)日：2017-05-02

申请号：US14930666

申请日：2015-11-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.

公开(公告)号：US20220342765A1

公开(公告)日：2022-10-27

申请号：US17337428

申请日：2021-06-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/14 ,  G06F11/07 ,  G06F11/30 ,  G06F1/30 ,  G06F12/02

Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.

公开(公告)号：US11409472B1

公开(公告)日：2022-08-09

申请号：US17214916

申请日：2021-03-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/02

Abstract: A trim command processing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a trim command from a host system, where the trim command is configured to indicate data stored in at least one logical address among a plurality of logical addresses can be erased; calculating a first data volume of data required to be programmed when a data trim operation is performed according to the trim command; and determining whether to perform a first trim operation or a second trim operation according to the first data volume.

公开(公告)号：US10101914B2

公开(公告)日：2018-10-16

申请号：US15093755

申请日：2016-04-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

IPC: G06F12/02 ,  G06F3/06

Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.

公开(公告)号：US09772797B2

公开(公告)日：2017-09-26

申请号：US15007222

申请日：2016-01-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0656 ,  G06F3/0617 ,  G06F3/0631 ,  G06F3/0679 ,  G06F12/0804 ,  G06F2212/222 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The method includes allocating a first zone and a second zone in the buffer memory for temporarily storing a plurality of logical address-physical address mapping tables and performing a restore operation on the first zone. The method also includes receiving a write command, wherein a logical address-physical address table to which a logical address indicated by the write command belongs has been temporarily stored in the first zone. The method further includes copying the logical address-physical address table into the second zone, and updating the logical address-physical address table in the second zone.

公开(公告)号：US20170228162A1

公开(公告)日：2017-08-10

申请号：US15093755

申请日：2016-04-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0605 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.