公开(公告)号：US20190189228A1

公开(公告)日：2019-06-20

申请号：US15890326

申请日：2018-02-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Hsiang Lin ,  Yu-Cheng Hsu

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C16/10

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

公开(公告)号：US20180101317A1

公开(公告)日：2018-04-12

申请号：US15361008

申请日：2016-11-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/04 ,  G06F3/0619 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  H03M13/2957

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.

公开(公告)号：US20170242748A1

公开(公告)日：2017-08-24

申请号：US15096284

申请日：2016-04-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin

IPC: G06F11/10 ,  H03M13/45 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/458 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

公开(公告)号：US09703698B2

公开(公告)日：2017-07-11

申请号：US13935572

申请日：2013-07-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Kim-Hon Wong ,  Hao-Zhi Lee ,  Hung-Chun Lin ,  Chun-Yen Chang

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C29/00 ,  G11C7/04

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C7/04 ,  G11C11/5628 ,  G11C29/82

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

公开(公告)号：US09583217B2

公开(公告)日：2017-02-28

申请号：US14296383

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G11C29/52 ,  H03M13/37 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/3746

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。

公开(公告)号：US20160350179A1

公开(公告)日：2016-12-01

申请号：US14818323

申请日：2015-08-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/08 ,  H03M13/45 ,  G11C29/52

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first memory cells according to a first soft-decision read voltage level to obtain a first soft-decision coding unit belonging to a block code; performing a first soft-decision decoding procedure for the first soft-decision coding unit; if the first soft-decision decoding procedure fails, reading the first memory cells according to a second soft-decision read voltage level to obtain a second soft-decision coding unit belonging to the block code, where a difference value between the first soft-decision read voltage level and the second soft-decision read voltage level is related to a wear degree of the first memory cells; and performing a second soft-decision decoding procedure for the second soft-decision coding unit. Accordingly, a decoding efficiency of block codes may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一软判决读取电压电平读取多个第一存储器单元以获得属于块码的第一软判决编码单元; 对所述第一软判决编码单元执行第一软判决解码过程; 如果第一软判决解码过程失败，则根据第二软判决读取电压电平读取第一存储器单元以获得属于块代码的第二软判决编码单元，其中第一软判决解码程序 读取电压电平，第二软判决读取电压电平与第一存储器单元的磨损程度相关; 以及对所述第二软判决编码单元执行第二软判决解码过程。 因此，可以提高块码的解码效率。

公开(公告)号：US09496041B2

公开(公告)日：2016-11-15

申请号：US14692759

申请日：2015-04-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Abstract translation: 提供了一种用于具有存储器单元的可重写非易失性存储器模块的存储器编程方法。 存储器编程方法包括：根据写数据对存储器单元执行第一编程处理并获得第一编程处理的第一编程结果; 根据第一编程结果将存储器单元分组成编程组; 以及根据写入数据对存储器单元执行第二编程处理。 第二编程过程包括：通过使用第一编程电压对编程组中的第一编程组进行编程; 以及通过使用第二编程电压来编程所述编程组中的第二编程组。 第一编程电压和第二编程电压不同。 此外，提供存储器控制电路单元和存储器存储装置。

公开(公告)号：US20160306693A1

公开(公告)日：2016-10-20

申请号：US14745472

申请日：2015-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/50

CPC classification number: G06F11/1048 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/5004

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

Abstract translation: 提供读取电压电平估计方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压电平读取可重写非易失性存储器模块的第一区域，以获得属于块码的第一编码单元; 对所述第一编码单元执行第一解码过程并记录第一解码信息; 根据第二读取电压电平读取第一区域以获得属于块码的第二编码单元; 对所述第二编码单元执行第二解码过程并记录第二解码信息; 以及根据第一解码信息和第二解码信息估计并获得第三读取电压电平。 因此，可以提高采用块代码的可重写非易失性存储器模块的管理能力。

公开(公告)号：US20150186212A1

公开(公告)日：2015-07-02

申请号：US14190103

申请日：2014-02-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：根据第一读取电压读取至少一个存储器单元以获得至少一个第一验证位; 执行根据第一验证位的硬比特模式解码过程，以及通过硬比特模式解码过程来确定是否产生第一有效码字; 如果第一有效码字不是由硬比特模式解码过程产生的，则获得存储单元的存储信息; 根据存储信息确定电压数; 根据与电压数相匹配的第二读取电压来读取存储器单元以获得第二验证位; 以及根据第二验证位执行软位模式解码过程。 因此，解码速度提高。

公开(公告)号：US20140226412A1

公开(公告)日：2014-08-14

申请号：US14257010

申请日：2014-04-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Wei Lin

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3418 ,  G11C16/3468 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/028 ,  G11C2211/5621

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of the memory storage apparatus. The method further includes adjusting at least one predetermined operation parameter corresponding to the rewritable non-volatile memory module to generate at least one adjusted operation parameter corresponding to the rewritable non-volatile memory module and writing the data into the memory cell based on the at least one adjusted operation parameter if the operating temperature of the memory storage apparatus is larger than a predetermined temperature. Accordingly, the method can accurately store data into the rewritable non-volatile memory module, thereby lowing the operating temperature of the memory storage apparatus.

Abstract translation: 一种用于将数据写入可重写非易失性存储器模块的存储单元的数据写入方法，以及使用相同区域的存储器控​​制电路单元和存储器存储装置。 该方法包括记录存储单元的磨损程度并检测存储器存储装置的工作温度。 该方法还包括调整与可重写非易失性存储器模块相对应的至少一个预定操作参数，以生成与可重写非易失性存储器模块对应的至少一个经调整的操作参数，并至少基于至少一个数据写入存储器单元 如果存储器存储装置的工作温度大于预定温度，则调节操作参数。 因此，该方法可以将数据精确地存储到可重写非易失性存储器模块中，从而降低存储器存储装置的工作温度。