公开(公告)号：US20180301365A1

公开(公告)日：2018-10-18

申请号：US15945341

申请日：2018-04-04

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/306

Abstract: Methods, assemblies, and equipment are described for bonding one or more die that may be of dissimilar thickness to a wafer. The die may be fabricated and singulated with a planarized oxide layer protecting from wafer dicing and handling debris one or more metallized post structures connecting to an integrated circuit. Face sides of the die are bonded to a first handle wafer, such that the respective post structures are aligned in a common plane. The substrate material back sides of the bonded die are then thinned to a uniform thickness and bonded to a second handle wafer. The assembly may then be flipped, and the first handle wafer and protective layer including potential dicing and handling debris removed. The post structures are revealed, resulting in a composite wafer assembly including the second handle and one or more uniformly thinned die mounted thereto.

公开(公告)号：US20250151444A1

公开(公告)日：2025-05-08

申请号：US19015141

申请日：2025-01-09

Applicant: Raytheon Company

Inventor： David J. Gulbransen ,  Sean P. Kilcoyne ,  Eric R. Miller ,  Matthew D. Chambers ,  Eric J. Beuville ,  Andrew E. Gin ,  Adam M. Kennedy

IPC: H10F39/00 ,  H01L21/66 ,  H01L23/00 ,  H10F39/18

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

公开(公告)号：US20240120242A1

公开(公告)日：2024-04-11

申请号：US17963937

申请日：2022-10-11

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L22/34 ,  H01L21/76898 ,  H01L22/14 ,  H01L23/481

Abstract: An integrated circuit wafer is produced to include a substrate comprising a conductive layer and an insulating layer. The wafer can further be produced to include one or more circuit TSVs formed at least partially through the substrate and associated with an integrated circuit (IC). A test structure configured to facilitate testing of the integrity of the one or more circuit TSVs can be formed on the wafer. The test structure can include a first test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate, and a second test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate. The first test TSV and the second test TSV can operate as witness TSVs to the operability of the circuit TSVs.

公开(公告)号：US11710756B2

公开(公告)日：2023-07-25

申请号：US16952783

申请日：2020-11-19

Applicant: RAYTHEON COMPANY

Inventor： Jamal I. Mustafa ,  Robert C. Anderson ,  John L. Vampola ,  Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1469 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1462

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

公开(公告)号：US11430753B2

公开(公告)日：2022-08-30

申请号：US16923332

申请日：2020-07-08

Applicant: Raytheon Company

Inventor： Eric R. Miller ,  Sean P. Kilcoyne ,  Michael V. Liguori ,  Michael J. Rondon

IPC: H01L21/66 ,  H01L23/00

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

公开(公告)号：US20220154359A1

公开(公告)日：2022-05-19

申请号：US17098560

申请日：2020-11-16

Applicant: Raytheon Company

Inventor： Michael J. Rondon ,  Jon Sigurdson ,  Eric R. Miller

IPC: C25D7/12 ,  C25D3/54 ,  C23C14/18

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.