公开(公告)号：US06748546B1

公开(公告)日：2004-06-08

申请号：US09670041

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06F126

CPC classification number: G06F1/206 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.

Abstract translation: 提供了一种用于控制计算机系统中的热循环的方法。 该方法包括接收将计算机系统从第一操作模式转换到第二操作模式的请求，其中在第二操作模式中消耗较少的功率。 确定计算机系统在第一和第二操作模式之间转换的历史速率，并且响应于历史速率小于第一预选设定值而允许所请求的转换，但是响应于历史速率更大而拒绝 比第一个预选设定值。

公开(公告)号：US06528974B1

公开(公告)日：2003-03-04

申请号：US09669357

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G05F1577

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

Abstract translation: 提供电源。 电源由第一电源模块，第二电源模块和控制器组成。 第一电源模块能够提供第一预选量的电力。 第二电源模块能够传递第二预选量的电力。 第一和第二功率模块耦合在一起，以能够传递与第一和第二预选量的功率有关的总量的功率。 控制器适于选择性地使得第一和第二功率模块能够以第一预选量，第二预选量和总量中的一种来供电。

公开(公告)号：US5790890A

公开(公告)日：1998-08-04

申请号：US608745

申请日：1996-02-29

Applicant: Russell N. Mirov ,  Victor Odisho

Inventor： Russell N. Mirov ,  Victor Odisho

IPC: G06F13/14 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06F17/00

CPC classification number: G06F11/2289 ,  G06F12/0684 ,  G06F15/177 ,  G06F9/4411

Abstract: An identification interface that transfers control information between a controller and an option module coupled to a motherboard of a computer. The identification interface supports the propagation of a plurality of bit fields containing information pertaining to the characteristics of the option module including, but not limited to, its speed, type and other information about its characteristics.

Abstract translation: 在控制器和耦合到计算机的主板的选件模块之间传送控制信息的识别接口。 识别接口支持包含与选项模块的特性有关的信息的多个位域的传播，包括但不限于其速度，类型和关于其特性的其它信息。

公开(公告)号：US06782480B2

公开(公告)日：2004-08-24

申请号：US09745976

申请日：2000-12-21

Applicant: Russell N. Mirov

Inventor： Russell N. Mirov

IPC: G06F126

CPC classification number: G06F12/1433

Abstract: An option module that may be installed in a computer system is provided. The option module includes functional circuitry that is accessed by the computer system through a conventional connector and/or bus. A nonvolatile memory is also included on the option module and is used to store a variety of system information, such as serial numbers. At least a portion of this system information is protected from alteration by the computer system. A second connector is also provided on the option module. An external device when coupled to the second connector may access all of the system data, and, if desired, alter it. Moreover, the option module need not be installed in the computer system for the external device to access the contents of the memory through the second connector.

Abstract translation: 提供了可以安装在计算机系统中的选项模块。 选件模块包括由计算机系统通过常规连接器和/或总线访问的功能电路。 非易失性存储器也包含在选件模块中，用于存储各种系统信息，如序列号。 该系统信息的至少一部分被保护以免被计算机系统的改变。 选件模块上还提供第二个连接器。 耦合到第二连接器时的外部设备可以访问所有系统数据，并且如果需要，可以改变它。 此外，选件模块不需要安装在计算机系统中，外部设备可以通过第二个连接器访问存储器的内容。

公开(公告)号：US06718473B1

公开(公告)日：2004-04-06

申请号：US09670420

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06R132

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.

Abstract translation: 在本发明的一个方面，提供了一种用于控制锁相环电路的操作的方法。 该方法包括监视系统时钟的频率，并且响应于系统时钟的检测频率大于预选设定点而递送第一信号。 响应于系统时钟的检测频率小于预先选定的设定点而递送第二信号。 响应于接收到第一信号来选择锁相环电路的第一操作模式。 第一种操作模式允许锁相环电路与第一预选频率范围内的时钟信号同步。 响应于接收到第二信号来选择锁相环电路的第二操作模式。 第二种操作模式允许锁相环电路与第二预选频率范围内的时钟信号同步。

公开(公告)号：US06573704B2

公开(公告)日：2003-06-03

申请号：US09745829

申请日：2000-12-21

Applicant: Russell N. Mirov

Inventor： Russell N. Mirov

IPC: G01R3126

CPC classification number: H05K1/0201 ,  G01K1/20 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/10151

Abstract: A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed circuit board is provided. Generally, a thermal isolation region, which may be comprised of a plurality of openings in the printed circuit board, is disposed about the temperature sensor to interrupt conductive transfer of heat from the heat generating component to the temperature sensor. The openings extend sufficiently far into the printed circuit board to remove at least a portion of a conductive layer, such as a power plane from the region surrounding the temperature sensor. Electrical power and signals may be provided to the temperature sensor through regions intermediate the openings.

公开(公告)号：US6008682A

公开(公告)日：1999-12-28

申请号：US664171

申请日：1996-06-14

Applicant: Russell N. Mirov

Inventor： Russell N. Mirov

IPC: G06F1/10 ,  H03L5/00

CPC classification number: G06F1/10

Abstract: A clock circuit for selectively enabling a clock signal to be propagated, via a transmission line, to an option module when the module is coupled to the clock circuit, and for preventing propagation of the clock signal through the transmission line when the option module is decoupled from the clock circuit. The clock circuit includes a clock driving element employed within a first module and a clock receiving element employed within a second module. The clock driving element includes a clock driver, normally an amplifier connected to at least one emitter-follower transistor. A pull-up resistor is coupled to the emitter of the transistor so that, when the option module is decoupled from the transmission line, the pull-up resistor applies voltage sufficient to turn-off the transistor. Otherwise, the pull-up resistor has no effect on the clock circuit.

Abstract translation: 一种时钟电路，用于当模块耦合到时钟电路时，选择性地使时钟信号经由传输线传播到选件模块，并且用于当选件模块解耦时防止时钟信号通过传输线的传播 从时钟电路。 时钟电路包括在第一模块内采用的时钟驱动元件和在第二模块内采用的时钟接收元件。 时钟驱动元件包括时钟驱动器，通常是连接到至少一个发射极跟随器晶体管的放大器。 上拉电阻器耦合到晶体管的发射极，使得当选件模块与传输线路分离时，上拉电阻器施加足以关断晶体管的电压。 否则，上拉电阻对时钟电路没有影响。

公开(公告)号：US5539328A

公开(公告)日：1996-07-23

申请号：US449450

申请日：1995-05-24

Applicant: Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

Inventor： Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  H03K17/16 ,  H03K19/003

CPC classification number: G06F11/1604 ,  G06F1/06 ,  H03L7/00 ,  G06F11/1608

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract translation: 为了最小化沿着印刷电路信号路径传送的信号施加的偏斜和抖动，在信号的信宿或接收元件附近形成终端电路。 终端电路可以是电阻性的，将信号路径耦合到电源和接地电位。

公开(公告)号：US5491442A

公开(公告)日：1996-02-13

申请号：US442851

申请日：1995-05-17

Applicant: Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

Inventor： Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00 ,  G06F1/04 ,  H03K3/00

CPC classification number: G06F11/1604 ,  G06F1/06 ,  H03L7/00 ,  G06F11/1608

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract translation: 时钟发生器通过将主时钟的延迟版本的分割应用于触发器的数据输入并对触发器进行计时，从主时钟和主时钟的延迟时钟版本产生多个时钟信号， 主时钟。 通过将触发器的输出施加到第二触发器阵列的数据输入（多个时钟信号中的每一个的阵列的一个触发器）中产生多个时钟信号，这些触发器被计时 通过主时钟的延迟版本。

公开(公告)号：US5461332A

公开(公告)日：1995-10-24

申请号：US289823

申请日：1994-10-03

Applicant: Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

Inventor： Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

CPC classification number: G06F11/1604 ,  G06F1/06 ,  H03L7/00 ,  G06F11/1608

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract translation: 用于产生用于分配到多个同步时钟的装置的多个多频数字时钟信号的时钟发生器系统包括两个分离的基本相同的结构的时钟发生器单元，其以锁定步骤一致地操作。 一个发生器单元的数字时钟信号输出被分配到同步时钟的装置和误差检测电路，该电路也接收来自其他时钟发生器单元的数字时钟信号，用于彼此比较。 在检测到错误的情况下，错误检测电路将产生一个错误信号，以停止使用时钟发生器系统的系统的操作，并复位时钟发生器。