公开(公告)号：US06728890B1

公开(公告)日：2004-04-27

申请号：US09670417

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06R126

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126

Abstract: A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

Abstract translation: 提供一种用于控制总线和与其耦合的部件的操作的方法。 该方法包括从耦合到总线的组件中的一个接收对总线事务的请求。 此后，提供给至少请求组件的时钟信号的频率增加，并且对所请求的总线事务进行维修。 在请求的总线事务完成时，提供给至少请求组件的时钟信号的频率降低。

公开(公告)号：US06691215B1

公开(公告)日：2004-02-10

申请号：US09670418

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06F1200

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

Abstract translation: 提供了一种存储系统。 存储器系统包括存储器，时钟信号发生器，锁相环电路和旁路电路。 时钟信号发生器产生第一时钟信号。 时钟信号发生器具有第一工作模式，其中第一时钟信号具有第一频率和第二工作模式，其中第一时钟信号具有第二频率。 锁相环电路与存储器相关联，并且适于接收第一时钟信号并向存储器提供同步的第二时钟信号。 旁路电路适于在第二操作模式中将第一时钟信号传送到存储器。

公开(公告)号：US06880970B2

公开(公告)日：2005-04-19

申请号：US10453752

申请日：2003-06-03

Applicant: Russell N. Mirov

Inventor： Russell N. Mirov

IPC: G01K1/20 ,  H05K1/02 ,  G01K1/00

CPC classification number: H05K1/0201 ,  G01K1/20 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/10151

Abstract: A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed circuit board is provided. Generally, a thermal isolation region, which may be comprised of a plurality of openings in the printed circuit board, is disposed about the temperature sensor to interrupt conductive transfer of heat from the heat generating component to the temperature sensor. The openings extend sufficiently far into the printed circuit board to remove at least a portion of a conductive layer, such as a power plane from the region surrounding the temperature sensor. Electrical power and signals may be provided to the temperature sensor through regions intermediate the openings.

Abstract translation: 提供了一种用于将安装在印刷电路板上的温度传感器与安装在印刷电路板上的发热部件进行热隔离的方法和装置。 通常，可以在印刷电路板中由多个开口组成的热隔离区域设置在温度传感器周围，以中断热量从发热部件到温度传感器的传导传递。 这些开口足够远地延伸到印刷电路板中以从包围温度传感器的区域移除至少一部分导电层，例如电源平面。 可以通过开口之间的区域向温度传感器提供电力和信号。

公开(公告)号：US06845457B1

公开(公告)日：2005-01-18

申请号：US09670419

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/28

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126

Abstract: A method is provided for controlling transitions between a first and second clock frequency signal in first and second components electrically coupled together and in communication with one another. The method comprises asserting a freeze signal to cause communications between the first and second components to cease. A freeze acknowledge signal is then received from the first and second components, indicating that communications therebetween have ceased. A change signal is delivered to the first and second components to cause the components to switch between the first and second clock frequency signals.

Abstract translation: 提供了一种用于控制第一和第二组件中的第一和第二时钟频率信号之间的转换的方法，所述第一和第二组件电耦合在一起并且彼此通信。 该方法包括断言冻结信号以使第一和第二组件之间的通信停止。 然后从第一和第二组件接收到冻结确认信号，表明它们之间的通信已经停止。 改变信号被传送到第一和第二分量，以使得分量在第一和第二时钟频率信号之间切换。

公开(公告)号：US06700421B1

公开(公告)日：2004-03-02

申请号：US09669825

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: H03L706

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal. The clock tree is coupled to receive the third clock signal and deliver at least one fourth clock signal. The feedback path is coupled to deliver the fourth clock signal to the second input terminal of the phase comparator.

Abstract translation: 提供了一个锁相环电路。 锁相环电路由第一和第二除N计数器，相位比较器，压控振荡器，时钟树和反馈路径组成。 第一分频计数器适于接收第一时钟信号并提供第二时钟信号。 相位比较器具有第一和第二输入端子和输出端子。 相位比较器适于比较施加到第一和第二输入端的信号的相位，并在输出端递送具有表示信号相位差的幅度的信号。 第一输入端耦合以接收第二时钟信号。 电压控制振荡器被耦合以接收相位差信号并传送具有对其响应的频率的第三时钟信号。 第二分频计数器被耦合以接收第三时钟信号并传送第四时钟信号。 时钟树被耦合以接收第三时钟信号并且递送至少一个第四时钟信号。 反馈路径被耦合以将第四时钟信号传送到相位比较器的第二输入端。

公开(公告)号：US06608476B1

公开(公告)日：2003-08-19

申请号：US09670143

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G01R1132

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.

Abstract translation: 提供一种用于通过监视电子设备的操作特性来操作电子设备的方法，以及根据所监视的操作特性来确定在第一，第二或第三操作模式下操作电子设备内的部件的至少一部分。 第一，第二和第三种操作模式以第一，第二和第三种不同的速率消耗功率。 指示部件的至少一部分在第一，第二和第三模式之间切换。

公开(公告)号：US5371417A

公开(公告)日：1994-12-06

申请号：US87556

申请日：1993-07-02

Applicant: Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

Inventor： Russell N. Mirov ,  Duc N. Le ,  Frank Mikalauskas ,  C. John Grebenkemper ,  Kinying Kwan

IPC: G06F1/12 ,  G06F1/06 ,  G06F11/16 ,  H03K5/15 ,  H03L7/00

CPC classification number: G06F11/1604 ,  G06F1/06 ,  H03L7/00 ,  G06F11/1608

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract translation: 用于产生用于分配到多个同步时钟的装置的多个多频数字时钟信号的时钟发生器系统包括两个分离的基本相同的结构的时钟发生器单元，其以锁定步骤一致地操作。 一个发生器单元的数字时钟信号输出被分配到同步时钟的装置和误差检测电路，该电路也接收来自其他时钟发生器单元的数字时钟信号，用于彼此比较。 在检测到错误的情况下，错误检测电路将产生一个错误信号，以停止使用时钟发生器系统的系统的操作，并复位时钟发生器。

公开(公告)号：US08970571B1

公开(公告)日：2015-03-03

申请号：US13419299

申请日：2012-03-13

Applicant: Adrian Wong ,  Russell N. Mirov

Inventor： Adrian Wong ,  Russell N. Mirov

IPC: G09G5/00

CPC classification number: G02B27/0172 ,  G02B27/0101 ,  G02B27/283 ,  G02B2027/0112 ,  G02B2027/0118 ,  G02B2027/014 ,  G02B2027/0178 ,  G02B2027/0194 ,  G02F1/133621 ,  G09G3/3406 ,  G09G3/3413 ,  G09G2320/0626 ,  G09G2320/064 ,  G09G2320/0666 ,  G09G2360/144 ,  G09G2360/145

Abstract: An apparatus includes a light source, a display array, a light relay, a photodetector, control circuitry, and measurement circuitry. The light source is for providing lamp light during an ON-time of the light source. The display array is positioned to receive and selectively manipulate the lamp light. The light relay is positioned to receive the image light from the display array. The photodetector is optically coupled to receive light. Control circuitry is coupled to the light source for cycling the light source and coupled to the measurement circuitry for coordinating light measurements of the photodetector.

Abstract translation: 一种装置包括光源，显示阵列，光继电器，光电检测器，控制电路和测量电路。 光源用于在光源的接通时间期间提供灯光。 显示阵列被定位成接收和选择性地操纵灯光。 光继电器被定位成从显示器阵列接收图像光。 光电检测器被光耦合以接收光。 控制电路耦合到光源，用于循环光源并耦合到测量电路，用于协调光电检测器的光测量。

公开(公告)号：US07514937B2

公开(公告)日：2009-04-07

申请号：US11284354

申请日：2005-11-21

Applicant: Russell N. Mirov ,  Howard L. Davidson

Inventor： Russell N. Mirov ,  Howard L. Davidson

IPC: G01R31/04 ,  G01R31/08

CPC classification number: G01R31/312 ,  G01R31/046 ,  G01R31/2812 ,  G01R31/2853

Abstract: A system configured to detect faults in signal lines. A system includes a first component configured to communicate with a second component via a signal path including one or more signal traces. Sense signal lines are manufactured such that at some point they are in close proximity to a signal trace which is to be monitored. The sense signal lines are configured to use parasitic coupling to redirect a portion of a signal conveyed via a signal trace to a monitoring component. The first component is configured to convey a test signal indicative of a type of test via the signal path, and a reference signal to the monitoring component. The monitoring component is configured to utilize the reference signal to ascertain a presence or absence, or characteristics of a received redirected signal. The monitoring component may optionally utilize a locally generated reference signal.

Abstract translation: 被配置为检测信号线路中的故障的系统。 系统包括被配置为经由包括一个或多个信号迹线的信号路径与第二部件通信的第一部件。 感测信号线被制造成使得在某些点处它们处于要被监控的信号迹线附近。 感测信号线被配置为使用寄生耦合来将经由信号迹线传送的信号的一部分重定向到监视部件。 第一组件被配置为经由信号路径传送指示测试类型的测试信号，以及向监视组件传送参考信号。 监视组件被配置为利用参考信号来确定所接收的重定向信号的存在或不存在或特性。 监视组件可以可选地利用本地生成的参考信号。

公开(公告)号：US06836824B1

公开(公告)日：2004-12-28

申请号：US09670368

申请日：2000-09-26

Applicant: Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

Inventor： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC: G06F1200

CPC classification number: G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Abstract translation: 提供了一种用于操作具有休眠模式的高速缓存的方法。 高速缓存位于计算机系统的存储器层次结构中，并且该方法包括接收第一高速缓存请求并且服务于第一高速缓存请求。 响应于完成第一高速缓存请求的服务而断言睡眠模式信号。 此后，接收到第二高速缓存请求，并且响应于接收到第二高速缓存请求，休眠模式信号被断言。 此后，服务第二高速缓存请求。