公开(公告)号：US11322401B2

公开(公告)日：2022-05-03

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame ,  Hiroki Niimi ,  Kandabara Tapily ,  Subhadeep Kal ,  Jodi Grzeskowiak ,  Anton Devilliers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

公开(公告)号：US11322350B2

公开(公告)日：2022-05-03

申请号：US16868277

申请日：2020-05-06

Applicant: Tokyo Electron Limited

Inventor： Daisuke Ito ,  Subhadeep Kal ,  Shinji Irie ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/027 ,  H01J37/32 ,  H01L21/67 ,  G03F7/20

Abstract: Embodiments provide a non-plasma etch, such as a gas-phase and/or remote plasma etch, of titanium-containing material layers with tunable selectivity to other material layers. A substrate is received within a process chamber, and the substrate has exposed material layers including a titanium-containing material layer and at least one additional material layer. The additional material layer is selectively etched with respect to the titanium-containing material layer by exposing the substrate to a controlled environment including a halogen-containing gas. For one embodiment, the halogen-containing gas includes a fluorine-based gas. For one embodiment, the titanium-containing material layer is a titanium or a titanium nitride material layer. For one embodiment, the additional material layer includes tungsten, tungsten oxide, hafnium oxide, silicon oxide, silicon-germanium, silicon, silicon nitride, and/or aluminum oxide. A non-selective etch with respect to the titanium-containing material layer can be performed by modulating the process parameters such as temperature.

公开(公告)号：US11264274B2

公开(公告)日：2022-03-01

申请号：US17010491

申请日：2020-09-02

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Hiroaki Niimi ,  Jodi Grzeskowiak ,  Daniel Chanemougame ,  Lars Liebmann ,  Kandabara Tapily ,  Subhadeep Kal ,  Anton J. deVilliers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

公开(公告)号：US10833078B2

公开(公告)日：2020-11-10

申请号：US16206513

申请日：2018-11-30

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara N. Tapily ,  Subhadeep Kal ,  Gerrit J. Leusink

IPC: H01L27/092 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L29/786 ,  H01L27/12

Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.

公开(公告)号：US20180040695A1

公开(公告)日：2018-02-08

申请号：US15671771

申请日：2017-08-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers ,  Nihar Mohanty ,  Subhadeep Kal ,  Kandabara Tapily

IPC: H01L29/06 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/0676 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further Includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

公开(公告)号：US09748110B2

公开(公告)日：2017-08-29

申请号：US15247138

申请日：2016-08-25

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Angelique D. Raley ,  Nihar Mohanty ,  Aelan Mosden

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

公开(公告)号：US20160379842A1

公开(公告)日：2016-12-29

申请号：US15191956

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67248

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Abstract translation: 描述了用于干燥去除微电子工件上的材料的方法。 该方法包括接收具有暴露由硅构成的目标层的表面和（1）有机材料或（2）氧和氮两者的表面的工件，并且从工件中选择性地去除目标层的至少一部分。 选择性去除包括将工件的表面暴露于含有N，H和F的化学环境处于第一设定点温度以化学改变目标层的表面区域，然后将工件的温度升高到第二设定点 温度以去除目标层的化学处理的表面区域。

公开(公告)号：US12272558B2

公开(公告)日：2025-04-08

申请号：US17964601

申请日：2022-10-12

Applicant: TOKYO ELECTRON LIMITED

Inventor： Matthew Flaugh ,  Jonathan Hollin ,  Subhadeep Kal ,  Pingshan Luan ,  Hamed Hajibabaeinajafabadi ,  Yu-Hao Tsai ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.

公开(公告)号：US20250069896A1

公开(公告)日：2025-02-27

申请号：US18453843

申请日：2023-08-22

Applicant: Tokyo Electron Limited

Inventor： Ivo Otto IV ,  Toshiki Kanaki ,  Jonathan Hollin ,  Subhadeep Kal

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.

公开(公告)号：US20240055268A1

公开(公告)日：2024-02-15

申请号：US17885228

申请日：2022-08-10

Applicant: TOKYO ELECTRON LIMITED

Inventor： Ivo Otto, IV ,  Subhadeep Kal

IPC: H01L21/311 ,  H01L21/02 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01L21/0217 ,  H01L21/02532 ,  H01J37/32449 ,  H01J2237/3341

Abstract: Etching is selectively performed and selectively is modified using a treatment or pre-treatment with nitrogen radicals, prior to etching. Etching is performed with a gas phase chemistry etch. Different selectivities can also be provided in different processes or different regions (or different devices or different locations) of a substrate by the selective use and non-use of the treatment.