SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20190172753A1

    公开(公告)日:2019-06-06

    申请号:US15859775

    申请日:2018-01-02

    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

    Semiconductor device and manufacturing method thereof
    13.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US09312356B1

    公开(公告)日:2016-04-12

    申请号:US14613379

    申请日:2015-02-04

    Abstract: The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.

    Abstract translation: 半导体器件包括栅电极,第一层间电介质,第一掩模层,第二掩模层和第二层间电介质。 第一层间电介质围绕栅电极的周边,并且第一掩模层设置在栅电极上。 第一掩模层和栅电极具有至少一个相同的金属成分。 第二掩模层设置在第一掩模层的侧壁上,第二层间电介质设置在第二掩模层上并与第一层间电介质直接接触。

    Method for fabricating patterned structure of semiconductor device
    15.
    发明授权
    Method for fabricating patterned structure of semiconductor device 有权
    制造半导体器件图案化结构的方法

    公开(公告)号:US08951918B2

    公开(公告)日:2015-02-10

    申请号:US13851113

    申请日:2013-03-27

    Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

    Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先,提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层,硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺,从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后,在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后,将图案化的硬掩模层用作蚀刻掩模,并且去除曝光的目标层,直到相应的基板的曝光。

    Method for fabricating semiconductor device

    公开(公告)号:US10312146B2

    公开(公告)日:2019-06-04

    申请号:US15647031

    申请日:2017-07-11

    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

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