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公开(公告)号：US10311950B2
公开(公告)日：2019-06-04
申请号：US15706356
申请日：2017-09-15
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
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12.发明授权Conductive metal oxide structures in non volatile re-writable memory devices 有权非易失性可重写存储器件中的导电金属氧化物结构公开(公告)号：US08848425B2
公开(公告)日：2014-09-30
申请号：US14023233
申请日：2013-09-10
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
CPC classification number: G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
Abstract translation: 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。
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公开(公告)号：US20140211542A1
公开(公告)日：2014-07-31
申请号：US14167694
申请日：2014-01-29
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
IPC: G11C13/00
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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公开(公告)号：US20210098063A1
公开(公告)日：2021-04-01
申请号：US17066198
申请日：2020-10-08
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
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公开(公告)号：US20180130946A1
公开(公告)日：2018-05-10
申请号：US15797452
申请日：2017-10-30
Applicant: Unity Semiconductor Corporation
Inventor： Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
CPC classification number: H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
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Patent Agency Ranking
公开(公告)号：US20180122857A1
公开(公告)日：2018-05-03
申请号：US15797716
申请日：2017-10-30
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
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公开(公告)号：US20170179197A1
公开(公告)日：2017-06-22
申请号：US15393545
申请日：2016-12-29
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
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18.发明申请CONDUCTIVE METAL OXIDE STRUCTURES IN NON-VOLATILE RE-WRITABLE MEMORY DEVICES 有权非易失性可写存储器件中的导电金属氧化物结构公开(公告)号：US20160267973A1
公开(公告)日：2016-09-15
申请号：US15075754
申请日：2016-03-21
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
CPC classification number: G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
Abstract translation: 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。
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公开(公告)号：US09293702B2
公开(公告)日：2016-03-22
申请号：US14476604
申请日：2014-09-03
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
CPC classification number: G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
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公开(公告)号：US20160005793A1
公开(公告)日：2016-01-07
申请号：US14850702
申请日：2015-09-10
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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