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公开(公告)号：US20140211542A1
公开(公告)日：2014-07-31
申请号：US14167694
申请日：2014-01-29
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
IPC: G11C13/00
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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公开(公告)号：US09806130B2
公开(公告)日：2017-10-31
申请号：US15393545
申请日：2016-12-29
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F. S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
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Patent Agency Ranking
公开(公告)号：US09570515B2
公开(公告)日：2017-02-14
申请号：US14850702
申请日：2015-09-10
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F. S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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公开(公告)号：US09159408B2
公开(公告)日：2015-10-13
申请号：US14167694
申请日：2014-01-29
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F. S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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公开(公告)号：US20180122857A1
公开(公告)日：2018-05-03
申请号：US15797716
申请日：2017-10-30
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
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公开(公告)号：US20170179197A1
公开(公告)日：2017-06-22
申请号：US15393545
申请日：2016-12-29
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
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公开(公告)号：US20160005793A1
公开(公告)日：2016-01-07
申请号：US14850702
申请日：2015-09-10
Applicant: Unity Semiconductor Corporation
Inventor： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
CPC classification number: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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