公开(公告)号：US09613967B1

公开(公告)日：2017-04-04

申请号：US15083302

申请日：2016-03-29

Applicant: Winbond Electronics Corp.

Inventor： Yi-Hao Chien ,  Yoshinori Tanaka ,  Wei-Che Chang

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10897

Abstract: A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A conductive layer is formed on the substrate in the second region. A top surface of the conductive layer is lower than a top surface of the first dielectric layer. A second dielectric layer is formed on the substrate. A portion of the second dielectric layer and a portion of the conductive layer are removed to form a first opening in the conductive layer and the second dielectric layer in the second region. The first opening exposes a surface of the substrate. A portion of the substrate in the second region is removed to form a trench in the substrate in the second region. A third dielectric layer is formed in the trench and the first opening.

公开(公告)号：US12193221B2

公开(公告)日：2025-01-07

申请号：US17340507

申请日：2021-06-07

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Kai Jen ,  Yu-Po Wang

IPC: H10B12/00

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

公开(公告)号：US12029049B2

公开(公告)日：2024-07-02

申请号：US17123513

申请日：2020-12-16

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Tse-Mian Kuo ,  Wei-Che Chang ,  Shuo-Che Chang

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H10N70/066 ,  H10N70/24 ,  H10N70/823 ,  H10N70/828 ,  H10N70/841

Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.

公开(公告)号：US11690214B2

公开(公告)日：2023-06-27

申请号：US17481772

申请日：2021-09-22

Applicant: Winbond Electronics Corp.

Inventor： Hung-Yu Wei ,  Pei-Hsiu Peng ,  Wei-Che Chang

IPC: H10B12/00 ,  H01L29/06

CPC classification number: H10B12/315 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/488

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

公开(公告)号：US11545493B2

公开(公告)日：2023-01-03

申请号：US17130883

申请日：2020-12-22

Applicant: Winbond Electronics Corp.

Inventor： Ying-Chu Yen ,  Wei-Che Chang

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L21/308 ,  H01L21/265 ,  H01L21/762 ,  H01L21/3105

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

公开(公告)号：US20220068939A1

公开(公告)日：2022-03-03

申请号：US17121765

申请日：2020-12-15

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L27/108

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

公开(公告)号：US20220028866A1

公开(公告)日：2022-01-27

申请号：US17498765

申请日：2021-10-12

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

IPC: H01L27/108 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

公开(公告)号：US10910384B2

公开(公告)日：2021-02-02

申请号：US16411584

申请日：2019-05-14

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Ying-Chu Yen ,  Wei-Che Chang

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L21/308 ,  H01L21/265 ,  H01L21/762 ,  H01L21/3105

Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

公开(公告)号：US10424586B2

公开(公告)日：2019-09-24

申请号：US15867079

申请日：2018-01-10

Applicant: Winbond Electronics Corp.

Inventor： Ying-Chu Yen ,  Wei-Che Chang ,  Yoshinori Tanaka

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

公开(公告)号：US20190019795A1

公开(公告)日：2019-01-17

申请号：US15997706

申请日：2018-06-05

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Huang-Nan Chen ,  Wei-Che Chang

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.