公开(公告)号：US20150311891A1

公开(公告)日：2015-10-29

申请号：US14294176

申请日：2014-06-03

Applicant: Maxchip Electronics Corp.

Inventor： Ming-Chi Kuo ,  Tsung-Chih Tsai ,  Jen-Yao Hsu

IPC: H03K17/14 ,  H03K17/687 ,  H03K17/16

CPC classification number: H03K17/145 ,  H03K17/063 ,  H03K17/162 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0054 ,  H03K2217/0081

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract translation: 提供了一种高压自举门驱动装置。 栅极驱动装置包括高端晶体管，低端晶体管，缓冲器，升压电容器和高电压耗尽晶体管。 高端晶体管接收第一电源电压。 缓冲器根据偏置电压向高端晶体管提供高端驱动信号。 升压电容器串联耦合在基极电压和偏置电压之间。 耗尽晶体管的第一端耦合到第二电源电压，耗尽型晶体管的第二端耦合到偏置电压，耗尽晶体管的控制端接收参考接地电压。

公开(公告)号：US08980703B2

公开(公告)日：2015-03-17

申请号：US14505510

申请日：2014-10-03

Applicant: Maxchip Electronics Corp.

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L21/84 ,  H01L29/78 ,  H01L29/76 ,  H01L29/66 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L29/66825 ,  H01L27/11517 ,  H01L27/11526 ,  H01L28/20

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。

公开(公告)号：US08907395B2

公开(公告)日：2014-12-09

申请号：US13244640

申请日：2011-09-25

Applicant: Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L29/78 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L29/66825 ,  H01L27/11517 ,  H01L27/11526 ,  H01L28/20

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。

公开(公告)号：US08895386B2

公开(公告)日：2014-11-25

申请号：US13632162

申请日：2012-10-01

Applicant: Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L21/8242

CPC classification number: H01L27/11541 ,  H01L27/0629 ,  H01L27/11524 ,  H01L27/11543 ,  H01L28/20 ,  H01L28/40

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 氧化物材料层和第一导电材料层依次形成在电池和周边区域的基板上。 执行图案化步骤以在基板和外围区域中分别在基板上形成第一和第二堆叠结构。 分别在第一和第二堆叠结构的侧壁上形成第一和第二间隔物。 在第一层叠结构旁边的基板中形成至少两个第一掺杂区域，在第二堆叠结构旁边的基板上形成两个第二掺杂区域。 至少在第一堆叠结构上形成电介质层和第二导电层。 电池区域中的第一堆叠结构，电介质层和第二导电层构成电荷存储结构。

公开(公告)号：US08163583B2

公开(公告)日：2012-04-24

申请号：US12721546

申请日：2010-03-10

Applicant: Tsai-Chiang Nieh ,  Tung-Ming Lai ,  Feng-Tsai Tsai

Inventor： Tsai-Chiang Nieh ,  Tung-Ming Lai ,  Feng-Tsai Tsai

IPC: H01L21/467

CPC classification number: B81C1/00944 ,  B81B3/0008 ,  B81C2203/0742

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract translation: 提供微电子机械系统结构及其制造方法。 衬底具有多个导电区域。 在基板上形成电介质层。 在电介质层中形成多个开口和凹槽，其中开口暴露导电区域。 凹槽位于开口之间。 在电介质层上形成导电层，并且用导电层填充开口和凹部。 导电层被图案化以在电介质层上形成多个第一导电图案的条带，并且在每个凹部的侧壁和底部上形成第二导电图案，其中第一导电图案通过第二导电图案彼此连接 。 去除电介质层。 去除第一导电图案之间的第二导电图案。

公开(公告)号：US20110140188A1

公开(公告)日：2011-06-16

申请号：US12635703

申请日：2009-12-11

Applicant: Chung-Yi Chen ,  Li-Yeat Chen ,  Jung-Chun Lin

Inventor： Chung-Yi Chen ,  Li-Yeat Chen ,  Jung-Chun Lin

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/1203 ,  H01L29/42324

Abstract: A non-volatile memory device including a substrate, a dielectric layer, a floating gate, source and drain regions, a channel region, and a doped layer is provided. The substrate includes a first region and a second region, and the substrate has an uneven surface in the second region. The dielectric layer is located on the substrate in the first region and in the second region to cover the uneven surface. The floating gate is located on the dielectric layer in the first region and is continuously extended to the second region. The source and drain regions are located in the substrate at opposite sides of the floating gate in the first region. The channel region is located in the substrate between the source and drain regions. The doped layer is located on the uneven surface or in the substrate in the second region to serve as a control gate.

Abstract translation: 提供了包括衬底，电介质层，浮动栅极，源极和漏极区域，沟道区域和掺杂层的非易失性存储器件。 衬底包括第一区域和第二区域，并且衬底在第二区域中具有不平坦的表面。 电介质层位于第一区域和第二区域中的衬底上以覆盖不平坦表面。 浮栅位于第一区域的介电层上，并连续延伸到第二区域。 源极和漏极区域位于第一区域中的浮动栅极的相对侧的衬底中。 沟道区位于源极和漏极区之间的衬底中。 掺杂层位于第二区域的不平坦表面或衬底中，用作控制栅极。

公开(公告)号：US09136301B2

公开(公告)日：2015-09-15

申请号：US14020908

申请日：2013-09-09

Applicant: Maxchip Electronics Corp.

Inventor： Jin-Wei Chang ,  Hung-Lung Wang ,  Jung-Kai Hung

IPC: H01L27/14 ,  H01L27/146 ,  G01J1/02 ,  G01J1/08 ,  G01J1/42 ,  H01L27/144 ,  G01J3/36 ,  G01J5/08

CPC classification number: H01L27/14649 ,  G01J1/02 ,  G01J1/029 ,  G01J1/08 ,  G01J1/4204 ,  G01J1/4228 ,  G01J3/36 ,  G01J5/0846 ,  H01L27/1443 ,  H01L27/14621 ,  H01L27/14652

Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

Abstract translation: 提供了与包括基板，IR感测结构，电介质层和多波段光感测结构的红外线（IR）感测功能相结合的多波段光束传感器。 衬底包括第一区域和第二区域。 IR感测结构位于用于感测IR的基板中。 电介质层位于IR感测结构上。 多波段光束感测结构包括第一波段光传感器，第二波段光传感器和第三波段光传感器。 第二波段光传感器和第一波段光传感器从底部向上叠置并设置在基板的第一区域上的IR感测结构上。 第三波段光传感器位于第二区域的介质层中。

公开(公告)号：US08558177B2

公开(公告)日：2013-10-15

申请号：US12696026

申请日：2010-01-28

Applicant: Jin-Wei Chang ,  Jen-Yao Hsu ,  Hong-Xian Wang ,  Yu-Hsien Chen

Inventor： Jin-Wei Chang ,  Jen-Yao Hsu ,  Hong-Xian Wang ,  Yu-Hsien Chen

IPC: G01J5/00

CPC classification number: G01J1/4228 ,  G01J1/02 ,  G01J1/029 ,  G01J1/08 ,  G01J1/4204 ,  G01J5/0846 ,  H01L27/1443

Abstract: An ambit light sensor with a function of IR sensing and a method of fabricating the same are provided. The ambit light sensor includes a substrate, an ambit light sensing structure, an infrared ray (IR) sensing structure, and a dielectric layer. The ambit light sensing structure is located over the substrate for sensing and filtering visible light. The IR sensing structure is located in the substrate under the ambit light sensing structure for sensing IR. The dielectric layer is located between the ambit light sensing structure and the IR sensing structure.

Abstract translation: 提供了一种具有IR感测功能的光束传感器及其制造方法。 该载流子传感器包括基板，横截面光感测结构，红外线（IR）感测结构和电介质层。 该位移光感测结构位于衬底上，用于感测和过滤可见光。 IR感测结构位于用于感测IR的光束感测结构下的衬底中。 电介质层位于光束感测结构和IR感测结构之间。

公开(公告)号：US08502328B2

公开(公告)日：2013-08-06

申请号：US13409020

申请日：2012-02-29

Applicant: Tsai-Chiang Nieh ,  Tung-Ming Lai ,  Feng-Tsai Tsai

Inventor： Tsai-Chiang Nieh ,  Tung-Ming Lai ,  Feng-Tsai Tsai

IPC: H01L29/84

CPC classification number: B81C1/00944 ,  B81B3/0008 ,  B81C2203/0742

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract translation: 提供微电子机械系统结构及其制造方法。 衬底具有多个导电区域。 在基板上形成电介质层。 在电介质层中形成多个开口和凹槽，其中开口暴露导电区域。 凹槽位于开口之间。 在电介质层上形成导电层，并且用导电层填充开口和凹部。 导电层被图案化以在电介质层上形成多个第一导电图案的条带，并且在每个凹部的侧壁和底部上形成第二导电图案，其中第一导电图案通过第二导电图案彼此连接 。 去除电介质层。 去除第一导电图案之间的第二导电图案。

公开(公告)号：US20120264264A1

公开(公告)日：2012-10-18

申请号：US13537038

申请日：2012-06-28

Applicant: Chung-Yi Chen ,  Li-Yeat Chen ,  Jung-Chun Lin

Inventor： Chung-Yi Chen ,  Li-Yeat Chen ,  Jung-Chun Lin

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/1203 ,  H01L29/42324

Abstract: A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region.

Abstract translation: 提供一种制造非易失性存储器件的方法。 提供了包括第一区域和第二区域的衬底。 然后，在第二区域中的基板上形成不平坦的表面。 此后，在第二区域中的衬底中形成掺杂层，并且掺杂层用作控制栅极。 之后，在第二区域的第一区域和基板的不平坦表面上的基板上形成电介质层。 接下来，在电介质层上形成浮栅，浮栅从第一区扩展到第二区。 源极和漏极区域在第一区域中的浮动栅极的相对侧的衬底中形成。