公开(公告)号：US12283481B2

公开(公告)日：2025-04-22

申请号：US17353547

申请日：2021-06-21

Applicant: United Microelectronics Corp.

Inventor： Yu Cheng Lin ,  Wei-Chuang Lai

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/00

Abstract: A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.

公开(公告)号：US20250126889A1

公开(公告)日：2025-04-17

申请号：US18505094

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： YUERAN QIAO ,  Yi Liu ,  Guohai Zhang ,  Genmao Liu ,  Lei Zhu

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: The invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises a silicon layer and an insulating layer stacked from bottom to top, a phosphosilicate glass (PGS) on the insulating layer, and a fluorosilicate glass (FSG) on the phosphosilicate glass. The probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

公开(公告)号：US12274175B2

公开(公告)日：2025-04-08

申请号：US17565496

申请日：2021-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a first inter-metal dielectric (IMD) layer on a substrate, a first metal interconnection in the first IMD layer, a second IMD layer on the first IMD layer, a second metal interconnection in the second IMD layer, a bottom electrode on the second metal interconnection, a magnetic tunneling junction (MTJ) on the bottom electrode, a top electrode on the MTJ, a cap layer adjacent to the MTJ, a third IMD layer on the MTJ, and a third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection. Preferably, a width of a bottom surface of the MTJ is less than a width of a top surface of the MTJ.

公开(公告)号：US12274081B2

公开(公告)日：2025-04-08

申请号：US18519099

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H10D30/47 ,  H01L21/311 ,  H10D30/01 ,  H10D62/85

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20250113742A1

公开(公告)日：2025-04-03

申请号：US18979539

申请日：2024-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US20250113605A1

公开(公告)日：2025-04-03

申请号：US18496941

申请日：2023-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Tien Chou ,  Gang Ren ,  Xingxing Chen ,  Ji Feng ,  Guohai Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/12

Abstract: A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.

公开(公告)号：US20250112184A1

公开(公告)日：2025-04-03

申请号：US18979653

申请日：2024-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.

公开(公告)号：US12268098B2

公开(公告)日：2025-04-01

申请号：US18528707

申请日：2023-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US12266723B2

公开(公告)日：2025-04-01

申请号：US18596643

申请日：2024-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

公开(公告)号：US12266696B2

公开(公告)日：2025-04-01

申请号：US18608890

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.