公开(公告)号：US11886307B2

公开(公告)日：2024-01-30

申请号：US17467292

申请日：2021-09-06

Applicant: VMware LLC

Inventor： Yang Yang ,  Ye Zhang ,  Wenguang Wang ,  Haifeng Li

IPC: G06F11/20 ,  G06F16/182 ,  G06F11/14

CPC classification number: G06F11/2007 ,  G06F11/1423 ,  G06F11/2028 ,  G06F11/2094 ,  G06F16/1834 ,  G06F2201/85

Abstract: The location of resources for file services are located within the same site, thereby eliminating or reducing performance issues caused by cross-site accesses in a stretched cluster environment. A file server placement algorithm initially places file servers at a site based at least in part on host workload and affinity settings, and can perform failover to move the file servers to a different location (e.g., to a different host on the same site or to another site) in the event of a failure of the host where the file servers were initially placed. File servers may be co-located with clients at a location based on client latencies and site workload. Failover support is also provided in the event that the sites in the stretched cluster have different subnet addresses.

公开(公告)号：US11880287B2

公开(公告)日：2024-01-23

申请号：US18062950

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F11/00 ,  G06F11/20

CPC classification number: G06F11/2025 ,  G06F11/2028 ,  G06F2201/85

Abstract: Embodiments described herein are generally directed to intelligent management of microservices failover. In an example, responsive to an uncorrectable hardware error associated with a processing resource of a platform on which a task of a service is being performed by a primary microservice, a failover trigger is received by a failover service. A secondary microservice is identified by the failover service that is operating in lockstep mode with the primary microservice. The secondary microservice is caused by the failover service to takeover performance of the task in non-lockstep mode based on failover metadata persisted by the primary microservice. The primary microservice is caused by the failover service to be taken offline.

公开(公告)号：US11842787B2

公开(公告)日：2023-12-12

申请号：US17902195

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Seungjune Jeon

IPC: G11C29/00 ,  G06F11/14 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C29/765 ,  G06F11/1076 ,  G06F11/1402 ,  G11C16/3404 ,  G11C29/52 ,  G06F2201/85

Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.

公开(公告)号：US11841780B1

公开(公告)日：2023-12-12

申请号：US17548264

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Rishi Baldawa ,  Shawn Patrick Jones

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/263 ,  H04L67/1074 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/2025 ,  G06F11/0709 ,  G06F11/263 ,  G06F11/3006 ,  H04L67/1074 ,  G06F11/203 ,  G06F2201/85

Abstract: A system is configured to simulate outages of network resources. The system is configured to provide a control plane for computing resources of a provider network. The control plane is configured to cause simulated outages of a primary region of the plurality of regions selected to host the plurality of different computing resources. During the simulated outages, the control plane moves respective workloads of the plurality of different computing resources to be performed in the one or more secondary networks and tracks a performance of the one or more secondary regions hosting the moved respective workloads of the plurality of computing resources. After completing individual ones of the simulated outages of the first network, the control plane moves the respective workloads of the plurality of different computing resources back to the primary region.

公开(公告)号：US11841778B2

公开(公告)日：2023-12-12

申请号：US17713097

申请日：2022-04-04

Applicant: HANGZHOU QULIAN TECHNOLOGY CO., LTD.

Inventor： Weiwei Qiu ,  Wei Li ,  Hao Duan ,  Fanglei Huang ,  Shuai Zhang ,  Lizhong Kuang

IPC: G06F11/00 ,  G06F11/20 ,  H04L41/0654

CPC classification number: G06F11/2023 ,  H04L41/0654 ,  G06F2201/85

Abstract: A method for active failure recovery of a single node improved based on PBFT algorithm is disclosed. The abnormal node first initiates a view change request, if (2f+1) view change requests containing the same view value cannot be received within a specified period of time, the abnormal node enters a state to be recovered, and the node to be recovered initiates a recovery request to all nodes of the whole network, waits for replies from normal nodes and counts the number of replies, calculates a height of stable checkpoint of the whole network after receiving replies contain the same view value from (2f+1) nodes, and update the state thereof to finally complete the recovery. This method solves an inherent problem in the PBFT algorithm that a failure in a single node cannot be recovered autonomously, so that a practicability of the PBFT algorithm is greatly improved.

公开(公告)号：US11841777B2

公开(公告)日：2023-12-12

申请号：US17956140

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Alberto Troia ,  Antonino Mondello

IPC: G06F11/00 ,  G06F11/20 ,  G06F13/40 ,  G11C16/26 ,  G06F11/07 ,  G06F11/16

CPC classification number: G06F11/201 ,  G06F11/0727 ,  G06F11/1666 ,  G06F13/4022 ,  G06F13/4027 ,  G11C16/26 ,  G06F2201/85

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

公开(公告)号：US11822445B2

公开(公告)日：2023-11-21

申请号：US18095245

申请日：2023-01-10

Applicant: Weka.IO Ltd

Inventor： Maor Ben Dayan ,  Omri Palmon ,  Liran Zvibel

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10

CPC classification number: G06F11/2094 ,  G06F11/1092 ,  G06F11/2033 ,  G06F2201/85

Abstract: Methods and systems are provided for rapid failure recovery for a distributed storage system for failures by one or more nodes.

公开(公告)号：US11803446B2

公开(公告)日：2023-10-31

申请号：US17109053

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang Seok Ki ,  Sungwook Ryu ,  Seontaek Kim ,  Changho Choi ,  Ehsan Najafabadi

IPC: G06F11/00 ,  G06F11/14 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F11/20 ,  G06F11/30 ,  G06F11/32 ,  G06F11/34 ,  G06F12/0882 ,  G06F12/1009

CPC classification number: G06F11/1428 ,  G06F3/065 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0649 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/0772 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1484 ,  G06F11/203 ,  G06F11/2089 ,  G06F11/2094 ,  G06F11/3034 ,  G06F11/3037 ,  G06F11/3072 ,  G06F11/327 ,  G06F11/3409 ,  G06F12/0882 ,  G06F12/1009 ,  G06F2201/85 ,  G06F2212/262

Abstract: A storage device, and a method for operating a storage device. In some embodiments, the storage device includes storage media, and the method includes: determining, by the storage device, that the storage device is in a first fault state from which recovery is possible by power cycling the storage device or by formatting the storage media; determining, by the storage device, that the storage device is in a second fault state from which partial recovery is possible by operating the storage device with reduced performance, with reduced capacity, or in a read-only mode; and operating the storage device with reduced performance, with reduced capacity, or in the read-only mode.

公开(公告)号：US11797405B2

公开(公告)日：2023-10-24

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06F11/2094 ,  G11C16/0483 ,  G11C16/08 ,  G06F2201/85 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11790219B2

公开(公告)日：2023-10-17

申请号：US17500374

申请日：2021-10-13

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Steven L. Teig ,  Kenneth Duong

IPC: G06N3/065 ,  G06N3/08 ,  G06N3/04 ,  H01L25/065 ,  G06F11/20 ,  G06N3/084 ,  G06F11/14 ,  G06N3/048 ,  G06N3/063 ,  G06N3/082 ,  H01L23/31 ,  H01L23/00 ,  H01L25/075 ,  H01L25/04 ,  H01L25/11 ,  H01L25/07 ,  H03K19/21

CPC classification number: G06N3/065 ,  G06F11/1423 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2051 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/3128 ,  H01L25/0657 ,  G06F2201/85 ,  H01L24/16 ,  H01L24/17 ,  H01L25/043 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/16235 ,  H03K19/21

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.