公开(公告)号：US20180081543A1

公开(公告)日：2018-03-22

申请号：US15269518

申请日：2016-09-19

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/0893

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

公开(公告)号：US09904555B2

公开(公告)日：2018-02-27

申请号：US15405173

申请日：2017-01-12

Applicant: INTEL CORPORATION

Inventor： Ruchira Sasanka

IPC: G06F9/44 ,  G06F12/06 ,  G06F1/32 ,  G06F11/34 ,  G06F12/02 ,  G06F15/78

CPC classification number: G06F9/4401 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/4411 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/023 ,  G06F12/0638 ,  G06F15/781 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/205 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Described herein are mechanisms for continuous automatic tuning of code regions for optimal hardware configurations for the code regions. One mechanism automatically tunes the tunable parameters for a demarcated code region by calculating metrics while executing the code region with different sets of tunable parameters and selecting one of the different sets based on the calculated metrics.

公开(公告)号：US09825980B2

公开(公告)日：2017-11-21

申请号：US15603925

申请日：2017-05-24

Applicant: AT&T Intellectual Property I, L.P.

Inventor： Cristina Serban

IPC: G06F15/173 ,  H04L29/06 ,  H04L12/26 ,  G06F11/34 ,  H04L29/08

CPC classification number: H04L63/1416 ,  G06F11/3466 ,  G06F2201/885 ,  H04L43/10 ,  H04L63/1425 ,  H04L67/1002 ,  H04L67/2842

Abstract: A content delivery network includes a plurality of cache servers. Each cache server is configured to receive a request for content from a client system and receive content and security data from a content server. Each cache server is further configured to provide the content to the client system and provide the security data to a monitoring system.

公开(公告)号：US09753831B2

公开(公告)日：2017-09-05

申请号：US13483618

申请日：2012-05-30

Applicant: Avi Kivity

Inventor： Avi Kivity

IPC: G06F12/10 ,  G06F11/34 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F11/3433 ,  G06F9/45558 ,  G06F9/5016 ,  G06F9/5022 ,  G06F11/348 ,  G06F12/10 ,  G06F2009/45583 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/885 ,  G06F2212/151

Abstract: A method and system for dynamically managing memory in a computing environment using a control monitor. The control monitor (e.g., a virtual machine monitor or operating system kernel) includes a nomination module configured to collect memory statistics associated with at least one memory node. Based on the memory statistics, the control monitor detects one or more first pages accessed from a remote memory node at or above an access threshold. The nomination module nominates, via a communication to at least one of a scheduler module and a memory manager of the control monitor, the one or more first pages for migration to the remote memory node.

公开(公告)号：US09734204B2

公开(公告)日：2017-08-15

申请号：US14567156

申请日：2014-12-11

Applicant: International Business Machines Corporation

Inventor： Richard N. Chamberlain ,  Howard J. Hellyer ,  Matthew F. Peters ,  Adam J. Pilkington

IPC: G06F12/02 ,  G06F12/12 ,  G06F17/30 ,  G06F12/0802 ,  G06F9/46

CPC classification number: G06F17/3048 ,  G06F9/46 ,  G06F11/3037 ,  G06F11/3409 ,  G06F11/36 ,  G06F11/3612 ,  G06F12/0802 ,  G06F2201/865 ,  G06F2201/885 ,  G06F2212/1044 ,  G06F2212/608 ,  G06F2212/7205

Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.

公开(公告)号：US20170185458A1

公开(公告)日：2017-06-29

申请号：US14998217

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Benjamin C. Chaffin ,  Robert J. Kyanko ,  Avinash Sodani

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F2201/885 ,  G06F2209/521

Abstract: Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.

公开(公告)号：US09678883B2

公开(公告)日：2017-06-13

申请号：US14335621

申请日：2014-07-18

Applicant: Futurewei Technologies, Inc.

Inventor： Tongping Liu ,  Chen Tian ,  Ziang Hu

IPC: G06F12/08 ,  G06F12/0891

CPC classification number: G06F11/3003 ,  G06F8/443 ,  G06F11/3037 ,  G06F11/3065 ,  G06F11/3089 ,  G06F11/3093 ,  G06F11/3428 ,  G06F11/3466 ,  G06F11/3471 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F2201/865 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/507

Abstract: In one embodiment, a method for detecting false sharing includes running code on a plurality of cores, where the code includes instrumentation and tracking cache invalidations in the code while running the code to produce tracked invalidations in accordance with the instrumentation, where tracking the cache invalidations includes tracking cache accesses to a plurality of cache lines by a plurality of tasks. The method also includes reporting false sharing in accordance with the tracked invalidations to produce a false sharing report.

公开(公告)号：US09667638B2

公开(公告)日：2017-05-30

申请号：US14938988

申请日：2015-11-12

Applicant: AT&T INTELLECTUAL PROPERTY I, L.P.

Inventor： Cristina Serban

IPC: G06F15/177 ,  G06F15/16 ,  H04L29/06 ,  H04L12/26 ,  H04L29/08 ,  G06F11/34

CPC classification number: H04L63/1416 ,  G06F11/3466 ,  G06F2201/885 ,  H04L43/10 ,  H04L63/1425 ,  H04L67/1002 ,  H04L67/2842

Abstract: A content delivery network includes a plurality of cache servers. Each cache server is configured to receive a request for content from a client system and receive content and security data from a content server. Each cache server is further configured to provide the content to the client system and provide the security data to a monitoring system.

公开(公告)号：US09632832B2

公开(公告)日：2017-04-25

申请号：US14758404

申请日：2014-02-27

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F9/50 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875

CPC classification number: G06F9/5033 ,  G06F9/4881 ,  G06F9/5027 ,  G06F11/34 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

Abstract: Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

公开(公告)号：US09626260B2

公开(公告)日：2017-04-18

申请号：US14723539

申请日：2015-05-28

Applicant: Jungwon University Industry Academy Cooperation Corps.

Inventor： Sung Hoon Baek

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/0891 ,  G06F11/14

CPC classification number: G06F11/2017 ,  G06F11/1435 ,  G06F11/1441 ,  G06F11/1471 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/123 ,  G06F2201/82 ,  G06F2201/885 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/222 ,  G06F2212/461 ,  G06F2212/466

Abstract: A read/write cache device and method persistent in the event of a power failure are disclosed herein. The read/write cache device includes a meta-information part, a recency/frequency (RF) table part, a mapping table part, and a log area. The meta-information part provides information about whether metadata has integrity and information about the version of metadata stored in two metadata regions. The RF table part provides information about the recency and frequency of each of low-speed segments of a plurality of high-speed and low-speed segments and information about whether each of the low-speed segments is cached, in order to maintain the consistency of the metadata. The mapping table part provides information about a low-speed segment that is cached to each of the high-speed segments. The log area provides changed caching information that is not applied into the mapping table part.