公开(公告)号：US09226400B2

公开(公告)日：2015-12-29

申请号：US13734266

申请日：2013-01-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masato Nomiya ,  Norio Sakai ,  Mitsuyoshi Nishide

IPC: H05K1/03 ,  H05K1/00 ,  H05K1/16 ,  H01R4/58 ,  H05K7/10 ,  H05K1/18 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/305 ,  H05K3/4626 ,  H05K3/4629 ,  H05K2201/0116 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: In a method for manufacturing a multilayer ceramic electronic device, a multilayer ceramic element assembly including laminated unsintered ceramic base material layers, a first conductor pattern, a seat portion disposed in a surface of the multilayer ceramic element assembly and arranged to mount a surface mount electronic device thereon, a second conductor pattern connected to the surface mount electronic device, and a resin introduction portion located outside a vertically projected region of the surface mount electronic device and arranged to introduce a resin to the seat portion is prepared. The multilayer ceramic element assembly is fired and the surface mount electronic device is mounted on the seat portion of the fired multilayer ceramic element assembly with the second conductor pattern therebetween. The resin is filled from the resin introduction portion into the seat portion and between the seat portion and the surface mount electronic device and is cured.

Abstract translation: 在多层陶瓷电子器件的制造方法中，包括层叠的未烧结的陶瓷基材层的多层陶瓷元件组件，第一导体图案，配置在所述多层陶瓷元件组件的表面的座部， 设置在其上，连接到表面安装电子设备的第二导体图案，以及位于表面安装电子设备的垂直投影区域外部并且布置成将树脂引入座部的树脂引入部分。 烧结多层陶瓷元件组件，并且表面安装电子器件安装在烧制的多层陶瓷元件组件的座部上，其间具有第二导体图案。 树脂从树脂引入部分填充到座椅部分中，并且在座椅部分和表面安装电子装置之间填充并固化。

公开(公告)号：US20150366076A1

公开(公告)日：2015-12-17

申请号：US14760605

申请日：2014-01-13

Applicant: BASF SE

Inventor： Harold Colwell ,  Inga Marie Balke ,  Lee Ann Dombrowski ,  Richard J. Lair ,  David M. Lange ,  Axel Wilms

IPC: H05K3/28 ,  H05K1/18 ,  B29C44/12 ,  B29C45/14 ,  B29C45/00

CPC classification number: B29C44/355 ,  B29C44/1266 ,  B29C44/1271 ,  B29C45/0013 ,  B29C45/14639 ,  B29C70/26 ,  B29C70/72 ,  B29K2077/00 ,  B29K2509/00 ,  B29L2031/3425 ,  H05K1/185 ,  H05K3/284 ,  H05K5/0034 ,  H05K5/065 ,  H05K2201/0116 ,  H05K2201/10151 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: An encapsulated electronic assembly comprises an electronic component and a foamed thermoplastic shell disposed about the electronic component. The foamed thermoplastic shell is formed from a thermoplastic encapsulant comprising a thermoplastic resin and a filler and is foamed with a foaming agent. A method of encapsulating the electronic component to form the encapsulated electronic assembly is also provided. The method includes the steps of melting the thermoplastic encapsulant, foaming the thermoplastic encapsulant, and injection molding the foamed thermoplastic encapsulant about the electronic component to form the foamed thermoplastic shell.

Abstract translation: 封装的电子组件包括围绕电子部件设置的电子部件和发泡热塑性壳体。 发泡热塑性壳体由热塑性树脂和填料组成的热塑性密封剂形成，并用发泡剂发泡。 还提供了一种封装电子部件以形成封装的电子组件的方法。 该方法包括熔化热塑性密封剂，使热塑性密封剂发泡，以及围绕电子部件注射成型发泡热塑性密封剂以形成发泡热塑性壳体的步骤。

公开(公告)号：US20150243609A1

公开(公告)日：2015-08-27

申请号：US14190745

申请日：2014-02-26

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H01L23/64 ,  H01L23/367 ,  H01L23/498 ,  H01L23/36 ,  H01L23/552 ,  H01L23/50

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract translation: 封装组件包括管芯堆叠和相关使用方法。 包装组件包括具有第一表面，第二表面和与从第一表面延伸到第二表面的通孔邻接的第三表面的基底。 组件还包括管芯叠层，导电层和盖。 芯片堆叠包括位于衬底中的通孔内的芯片。 导电层的一部分设置在基板的第三表面上。 盖的一部分设置在第一芯片和导电层的部分之间。 导电层被配置为与电力耦合，并且盖被配置为与地耦合。 盖的部分可以用作电容器的第一板，并且导电层的部分可以用作电容器的第二板。

公开(公告)号：US20150143925A1

公开(公告)日：2015-05-28

申请号：US14406346

申请日：2013-06-10

Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Inventor： Hugues Vandeparre ,  Stephanie Lacour

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  G01L1/14

CPC classification number: H05K1/0271 ,  G01L1/142 ,  H03K2017/9602 ,  H05K1/0373 ,  H05K1/09 ,  H05K2201/0116 ,  Y10T29/49117

Abstract: Stretchable electronic structure comprising one intrinsically fragile thin film integrated on or within a soft heterogeneous substrate. The invention also relates to a process for manufacturing such a structure.

Abstract translation: 可伸缩的电子结构包括集成在软质非均质基底上或内部的本质上易碎的薄膜。 本发明还涉及制造这种结构的方法。

公开(公告)号：US09013893B2

公开(公告)日：2015-04-21

申请号：US13896436

申请日：2013-05-17

Applicant: Industrial Technology Research Institute

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/16 ,  H01L23/50 ,  H01L23/00 ,  H05K3/46 ,  H01G4/33

CPC classification number: H05K1/185 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2203/0315

Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.

Abstract translation: 嵌入式电容器模块包括电极引出部分和与电极引出部分相邻设置的至少一个固体电解电容器部分。 电极引出部包括第一基板，第二基板，设置在第一基板和第二基板之间的第一绝缘材料，形成在第一基板的至少一个表面上的第一多孔层和设置在第一基板 在第一多孔层上。 固体电解电容器部分包括第一衬底，第二衬底，第一多孔层，第一氧化物层，它们全部从电极引出部分延伸出来，第一导电聚合物层设置在第一氧化物层上， 设置在第一导电聚合物层上的第一碳层和设置在第一碳层上的第一导电粘合剂层。

公开(公告)号：US20150034364A1

公开(公告)日：2015-02-05

申请号：US14162769

申请日：2014-01-24

Applicant: Zhen Ding Technology Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd.

Inventor： MING-JAAN HO ,  XIAN-QIN HU ,  SHAO-HUA WANG ,  FU-YUN SHEN

IPC: H05K1/02

CPC classification number: H05K1/0215 ,  H05K1/0216 ,  H05K1/0393 ,  H05K3/288 ,  H05K2201/0116 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/2009 ,  H05K2203/0221 ,  H05K2203/095 ,  H05K2203/1194

Abstract: An FPCB includes a flexible base, a wiring layer formed on a top surface of the base, a covering layer formed on the wiring layer, and a shielding layer formed on a portion of the covering layer. The wiring layer includes a grounding line. The covering layer defines an opening to expose the grounding line to the outside. A portion of the shielding layer fills into the opening. The shielding layer is electrically connected to the grounding line through the opening.

Abstract translation: FPCB包括柔性基底，形成在基底的顶表面上的布线层，形成在布线层上的覆盖层和形成在覆盖层的一部分上的屏蔽层。 布线层包括接地线。 覆盖层限定了将接地线暴露于外部的开口。 屏蔽层的一部分填充到开口中。 屏蔽层通过开口与接地线电连接。

公开(公告)号：US20140374141A1

公开(公告)日：2014-12-25

申请号：US14345352

申请日：2012-11-27

Applicant: Taiwan Green Point Enterprises Co., Ltd. ,  Jabil Circuit Inc.

Inventor： Sheng-Hung Yi ,  Pen-Yi Liao ,  Min-Hsiang Chen

IPC: H05K3/02 ,  H05K3/18 ,  H05K1/02

CPC classification number: H05K1/09 ,  H05K1/0296 ,  H05K3/027 ,  H05K3/182 ,  H05K3/188 ,  H05K3/242 ,  H05K3/243 ,  H05K3/381 ,  H05K2201/0116 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/108 ,  H05K2203/175

Abstract: A method for fabricating a conductive trace structure includes the steps: forming a first metal layer on a non-conductive substrate; removing a part of the first metal layer to expose the non-conductive substrate so as to form the first metal layer into a plating region and a non-plating region, the plating region being divided into at least two trace-forming portions and at least one bridge portion; forming a second metal layer on the plating region by electroplating the plating region using one of the trace-forming portions and the bridge portion as an electrode; and removing the bridge portion and the second metal layer formed on the bridge portion.

Abstract translation: 制造导电迹线结构的方法包括以下步骤：在非导电衬底上形成第一金属层; 去除所述第一金属层的一部分以暴露所述非导电基板，以便将所述第一金属层形成为电镀区域和非电镀区域，所述电镀区域被划分为至少两个迹线形成部分和至少 一个桥梁部分; 通过使用所述迹线形成部分和所述桥接部分之一通过电镀所述电镀区域作为电极在所述电镀区域上形成第二金属层; 以及去除桥接部分上形成的桥接部分和第二金属层。

公开(公告)号：US08822834B2

公开(公告)日：2014-09-02

申请号：US13187830

申请日：2011-07-21

Applicant: Shinichi Inoue ,  Hiroyuki Hanazono ,  Mineyoshi Hasegawa

Inventor： Shinichi Inoue ,  Hiroyuki Hanazono ,  Mineyoshi Hasegawa

IPC: H05K1/00

CPC classification number: H05K3/108 ,  H05K1/0274 ,  H05K1/0393 ,  H05K3/28 ,  H05K2201/0116 ,  H05K2201/2054

Abstract: A printed circuit board includes a base insulating layer formed of a porous film. Conductor traces are formed on the base insulating layer formed of the porous film. A cover insulating layer is formed on the base insulating layer to cover the conductor traces. The porous film used as the base insulating layer has a reflectivity of not less than 50% for light of at least a part of wavelengths in a wavelength region from 400 nm to 800 nm.

Abstract translation: 印刷电路板包括由多孔膜形成的基底绝缘层。 在由多孔膜形成的基底绝缘层上形成导体迹线。 在绝缘绝缘层上形成覆盖导体迹线的覆盖绝缘层。 用作基底绝缘层的多孔膜对于在400nm至800nm的波长区域中的至少一部分波长的光具有不小于50％的反射率。

公开(公告)号：US20140154427A1

公开(公告)日：2014-06-05

申请号：US13692570

申请日：2012-12-03

Applicant: NCC NANO, LLC

Inventor： ANDREW E. EDD ,  CHARLES C. MUNSON

IPC: H01B13/00

CPC classification number: H05K1/0386 ,  H05K1/092 ,  H05K3/106 ,  H05K3/12 ,  H05K3/1275 ,  H05K3/14 ,  H05K2201/0116 ,  H05K2203/0143 ,  H05K2203/0278 ,  H05K2203/1157 ,  H05K2203/121 ,  H05K2203/125 ,  H05K2203/1338 ,  H05K2203/1492

Abstract: A method for forming thin film conductors is disclosed. A thin film precursor material is initially deposited onto a porous substrate. The thin film precursor material is then irradiated with a light pulse in order to transform the thin film precursor material to a thin film such that the thin film is more electrically conductive than the thin film precursor material. Finally, compressive stress is applied to the thin film and the porous substrate to further increase the thin film's electrical conductivity.

Abstract translation: 公开了一种用于形成薄膜导体的方法。 最初将薄膜前体材料沉积到多孔基材上。 然后用光脉冲照射薄膜前体材料，以便将薄膜前体材料转变成薄膜，使得薄膜比薄膜前体材料更具导电性。 最后，对薄膜和多孔基材施加压应力，进一步提高薄膜的电导率。

公开(公告)号：US08692281B2

公开(公告)日：2014-04-08

申请号：US13271986

申请日：2011-10-12

Applicant: Wen-Herng Su ,  Junying Lu ,  Ho-Shang Lee

Inventor： Wen-Herng Su ,  Junying Lu ,  Ho-Shang Lee

IPC: H01L33/00

CPC classification number: H01L33/483 ,  H01L33/005 ,  H01L33/60 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/053 ,  H05K1/162 ,  H05K1/183 ,  H05K2201/0116 ,  H05K2201/0179 ,  H05K2201/10106 ,  H05K2203/0315 ,  Y10S362/80 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/53113 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.

Abstract translation: 本发明涉及发光二极管或LED电路的热管理，光提取和成本效益。 描述了集成电路LED基座，用于大功率LED的封装。 LED基座提供高导热性，同时保持电气绝缘。 特别地，描述了用于阳极氧化高导热性铝合金板以形成多孔氧化铝层和无孔氧化铝层的工艺。 该阳极氧化铝合金板作为优异的电绝缘体，并且还提供用于制造高密度和大功率多电平电路的表面形态和机械性能。