公开(公告)号：US20140349496A1

公开(公告)日：2014-11-27

申请号：US14287573

申请日：2014-05-27

Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： JIAN-JUN ZHU ,  JERRY WU

IPC: H01R13/646

CPC classification number: H01R13/6471 ,  H01R9/034 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/117 ,  H05K2201/09336 ,  H05K2201/09409 ,  H05K2201/10356

Abstract: A plug connector (100) includes a shell (10) and a printed circuit board (20) received in the shell. The printed circuit board includes a grounding layer (22), a conductive layer (21) disposed at a first side of the grounding layer, and an insulative layer (23) disposed therebetween. The conductive layer includes a pair of grounding traces (210), and a signal channel disposed between and isolated with the grounding traces. The signal channel includes a signal mating portion (221) disposed at a front portion. Each of the grounding traces includes a grounding mating portion (211) disposed at a front portion. Each of the grounding mating portions has a front end extending beyond the signal mating portion. The printed circuit board includes a pair of connecting traces (214). Each of the front ends of the grounding mating portions directly connects with the grounding layer by corresponding one of the connecting traces.

Abstract translation: 插头连接器（100）包括壳体（10）和容纳在外壳中的印刷电路板（20）。 印刷电路板包括接地层（22），设置在接地层的第一侧的导电层（21）和设置在其间的绝缘层（23）。 导电层包括一对接地迹线（210），以及设置在接地迹线之间并与接地迹线隔离的信号通道。 信号通道包括设置在前部的信号配合部分（221）。 每个接地迹线包括设置在前部的接地配合部分（211）。 每个接地配合部分具有延伸超过信号配合部分的前端。 印刷电路板包括一对连接迹线（214）。 接地配合部分的每个前端通过相应的一个连接迹线与接地层直接连接。

公开(公告)号：US08836138B2

公开(公告)日：2014-09-16

申请号：US13592547

申请日：2012-08-23

Applicant: Tomoharu Fujii

Inventor： Tomoharu Fujii

IPC: H01L29/40 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K3/46 ,  H05K1/16

CPC classification number: H01L23/50 ,  H01L23/49827 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a flat-plate shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a flat-plate shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a first signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.

Abstract translation: 布线基板包括：由无机材料制成的基板主体; 具有平板状的第一电极部，其沿着所述基板主体的厚度方向穿过所述基板主体; 具有平板形状的第二电极部分，其以厚度方向穿过所述基板主体并以规定的间隔面对所述第一电极部分; 以及第一信号电极，其设置在所述第一电极部分和所述第二电极部分之间，并且在所述厚度方向上穿过所述基板主体，其中所述第一电极部分和所述第二电极部分中的一个是接地电极，而另一个是 电源电极。

公开(公告)号：US20140054066A1

公开(公告)日：2014-02-27

申请号：US13956478

申请日：2013-08-01

Applicant: MStar Semiconductor, Inc.

Inventor： Tien Hua Yu ,  Shih Wei Lin

IPC: H05K1/02 ,  G06F17/50

CPC classification number: H05K1/0213 ,  G06F17/5068 ,  G06F17/5077 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/025 ,  H05K2201/09336

Abstract: A circuit layout method for a printed circuit board (PCB) is provided. The method includes forming a pair of signal traces on the PCB, and disposing a ground trace between the pair of signal traces. The pair of signal traces and the ground trace are located at a same layer of the PCB, and the ground trace renders the pair of transmission traces to have predetermined impedance. An associated PCB is also provided. The PCB includes a circuit layer, and a ground layer for grounding. The circuit layer includes a pair of signal traces, and a ground grace disposed between the pair of signal traces. The circuit layer is different from the ground layer. Based on the circuit layout method and the associated PCB, an electronic apparatus not only complies with mobile high-definition link (MHL) requirements regarding impedance between signal traces but also offers reduced costs.

Abstract translation: 提供了一种用于印刷电路板（PCB）的电路布局方法。 该方法包括在PCB上形成一对信号迹线，并在该对信号迹线之间设置接地迹线。 该对信号迹线和接地迹线位于PCB的同一层，并且接地迹线使该对传输迹线具有预定的阻抗。 还提供了相关的PCB。 PCB包括电路层和用于接地的接地层。 电路层包括一对信号迹线和布置在该对信号迹线之间的接地宽度。 电路层与地层不同。 基于电路布局方法和相关的PCB，电子设备不仅符合关于信号迹线之间的阻抗的移动高清晰度链路（MHL）要求，而且还降低了成本。

公开(公告)号：US20130106528A1

公开(公告)日：2013-05-02

申请号：US13664358

申请日：2012-10-30

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Romero Christian ,  Seung Wook Park ,  Young Do Kweon ,  Mi Jin Park

IPC: H03H7/38 ,  H05K3/00

CPC classification number: H05K1/0251 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09336

Abstract: Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.

Abstract translation: 本文公开了不对称多层基板，RF模块和用于制造非对称多层基板的方法。 不对称多层基板包括芯层，形成在芯层的一侧上并包括第一信号线图案的第一图案层，形成在另一侧上的第二图案层，并且包括第二金属板和第二布线线图案 ，比形成在第二图案层上的芯层薄且包括第一通孔的第一绝缘层和形成在第一绝缘层上并包括第三信号线图案的第三图案层，其中阻抗变换电路包括阻抗负载 并且形成传输线上的寄生电容负载用于在形成在芯层的上侧和下侧方向上的信号线图案之间的信号传输中的阻抗匹配。

公开(公告)号：US08385079B2

公开(公告)日：2013-02-26

申请号：US12624552

申请日：2009-11-24

Applicant: Jae-Hoon Choi ,  Jae-Seon Hwang ,  Hyo-Jae Bang ,  Hai-Young Lee

Inventor： Jae-Hoon Choi ,  Jae-Seon Hwang ,  Hyo-Jae Bang ,  Hai-Young Lee

IPC: H05K7/00

CPC classification number: H01L23/49827 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K1/025 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/09336 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0278

Abstract: A pressure conductive sheet includes a connector body formed of a thin plate of insulation material, an elastic body deposited as one body with the connector body, pluralities of connection terminals provided with a given interval to pass through the elastic body and the connector body, and a ground plate constituting a matching circuit, the ground plate being buried by a given width in between the connector body and the elastic body. The ground plate is coupled to a ground terminal among the connection terminals and is separated from an outer circumference face of a signal terminal. The connector body, the elastic body, the connection terminals and the ground plate are combined with one another to substantially reduce an interference between signal terminals through the matching circuit formed based on capacitance of a gap between a ground face of the ground plate and the signal terminal, and to improve electrical characteristics.

Abstract translation: 压力传导片包括由绝缘材料薄板形成的连接器主体，与连接器本体一体地沉积的弹性体，设置有给定间隔的多个连接端子以穿过弹性体和连接器主体，以及 构成匹配电路的接地板，接地板在连接器主体和弹性体之间被掩埋一定宽度。 接地板与连接端子之间的接地端子连接，并与信号端子的外周面分离。 连接器主体，弹性体，连接端子和接地板彼此组合，以通过基于接地板的接地面和信号之间的间隙的电容形成的匹配电路来大大减小信号端子之间的干扰 端子，并提高电气特性。

公开(公告)号：US20120285009A1

公开(公告)日：2012-11-15

申请号：US13556274

申请日：2012-07-24

Applicant: Kwan-Ho KIM ,  Ick-Kyu JANG ,  Ji-Man MYEONG

Inventor： Kwan-Ho KIM ,  Ick-Kyu JANG ,  Ji-Man MYEONG

IPC: H05K3/00

CPC classification number: H05K1/0219 ,  G09G3/3696 ,  G09G2330/06 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: A printed circuit board (“PCB”) includes a first pattern structure, a second pattern structure, a third pattern structure, and a fourth pattern structure. The first pattern structure includes a first ground pattern. The second pattern structure includes a first line pattern overlapping the first ground pattern and a second ground pattern electrically insulated from the first line pattern. The third pattern structure includes a third ground pattern overlapping the first line pattern and a second line pattern overlapping the second ground pattern. The fourth pattern structure includes a fourth ground pattern overlapping the second line pattern. Therefore, the PCB may decrease noise.

Abstract translation: 印刷电路板（PCB）包括第一图案结构，第二图案结构，第三图案结构和第四图案结构。 第一图案结构包括第一接地图案​​。 第二图案结构包括与第一接地图案​​重叠的第一线图案和与第一线图案电绝缘的第二接地图案。 第三图案结构包括与第一线图案重叠的第三接地图案和与第二接地图案重叠的第二线图案。 第四图案结构包括与第二线图案重叠的第四接地图案。 因此，PCB可能会降低噪音。

公开(公告)号：US08283572B2

公开(公告)日：2012-10-09

申请号：US12868686

申请日：2010-08-25

Applicant: Guang-Feng Ou ,  Yong-Zhao Huang

Inventor： Guang-Feng Ou ,  Yong-Zhao Huang

IPC: H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K2201/09336 ,  H05K2201/09618

Abstract: A printed circuit board includes a reference layer configured to connect to a power or a ground and a dielectric layer stacked on the reference layer. The dielectric layer includes a component surface opposing the reference layer. The component surface forms a differential pairs, a protection runner, and a power runner. The differential pairs include a substantially linear part. The protection runner is intervened between the linear part and the power runner, and is substantially parallel to the differential pairs. The length of the protection runner is approximately equal to that of the linear part. Each of the two ends of the protection runner forms a via that electrically connects the protection runner to the reference layer.

Abstract translation: 印刷电路板包括被配置为连接到电源或接地的参考层和堆叠在参考层上的电介质层。 电介质层包括与参考层相对的部件表面。 部件表面形成差速对，保护转轮和动力转轮。 差分对包括基本线性的部分。 保护跑步者介于线性部分和动力转轮之间，并且基本上平行于差速对。 保护流道的长度大致等于直线部分的长度。 保护流道的两端中的每一端形成将保护流道电连接到参考层的通孔。

公开(公告)号：US20120174047A1

公开(公告)日：2012-07-05

申请号：US13417879

申请日：2012-03-12

Applicant: Francesco Preda ,  Lloyd A. Walls

Inventor： Francesco Preda ,  Lloyd A. Walls

IPC: G06F17/50

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所得到的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

公开(公告)号：US08174843B2

公开(公告)日：2012-05-08

申请号：US12522100

申请日：2008-06-04

Applicant: Seiji Hayashi

Inventor： Seiji Hayashi

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract translation: 电源端子和半导体集成电路的接地端子通过电容器连接到导体图案。 导体图案通过滤波器连接到不与接地平面和电源平面连接的平面导体。 因此，引起从电源和地之间产生的共模噪声流入平面导体。 这降低了相对地充当天线的在地面和印刷电路板的电源中流动的共模噪声。

公开(公告)号：US08072774B2

公开(公告)日：2011-12-06

申请号：US12078019

申请日：2008-03-26

Applicant: Tomokazu Tokoro

Inventor： Tomokazu Tokoro

IPC: H05K1/03

CPC classification number: H01P3/08 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/09672 ,  H01L2224/0401

Abstract: An apparatus includes a substrate which includes an electronic component mounted on the substrate, the electronic component for processing a pair of signals, the substrate including a first wire for transmitting one of the signals, the first wire being formed on a first layer of the substrate, and a second wire for transmitting another one of the signals, the second wire being formed on a second layer of the substrate in a first region under the electronic component and being formed on a third layer in a second region of an other part of the first region.

Abstract translation: 一种装置包括：基板，其包括安装在基板上的电子部件，用于处理一对信号的电子部件，所述基板包括用于传输所述信号之一的第一布线，所述第一布线形成在所述基板的第一层上 以及用于传输另一个信号的第二线，所述第二线形成在所述电子部件下方的第一区域中的所述基板的第二层上，并且形成在所述第二层中的所述第二层中， 第一区。