公开(公告)号：US20130033284A1

公开(公告)日：2013-02-07

申请号：US13647585

申请日：2012-10-09

Applicant: SanDisk Technologies Inc.

Inventor： Arie Frenklakh

IPC: G01R31/26

CPC classification number: H05K1/0268 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07732 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0275 ,  H05K2201/09936 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

公开(公告)号：US08283664B2

公开(公告)日：2012-10-09

申请号：US13041895

申请日：2011-03-07

Applicant: Arie Frenklakh

Inventor： Arie Frenklakh

IPC: H01L23/58 ,  H01L29/10

CPC classification number: H05K1/0268 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07732 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0275 ,  H05K2201/09936 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

Abstract translation: 公开了一种形成半导体封装的方法，包括伪装测试焊盘。 测试焊盘被限定在半导体封装的导电图案中，用于允许完成封装的电测试。 测试垫形成为诸如字母或物体的形状，使得它们不太可识别为测试垫。

公开(公告)号：US20120087099A1

公开(公告)日：2012-04-12

申请号：US13195289

申请日：2011-08-01

Applicant: Taeho Moon ,  Whasu Sin ,  Junsoo Han ,  Jee-Min Park

Inventor： Taeho Moon ,  Whasu Sin ,  Junsoo Han ,  Jee-Min Park

IPC: H05K7/02

CPC classification number: H05K1/0269 ,  H01L23/13 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K2201/09936 ,  H05K2201/10159 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a printed circuit board for a board-on-chip package prepared with a strip level of a plurality of unit substrates and including a reject marking portion for determining whether there is a defective unit substrate, wherein the reject marking portion is in each unit substrate.

Abstract translation: 提供了一种用于片上芯片封装的印刷电路板，其制备有多个单元基板的带状层，并且包括用于确定是否存在缺陷单元基板的拒收标记部分，其中拒收标记部分在每个单元中 基质。

公开(公告)号：US08097816B2

公开(公告)日：2012-01-17

申请号：US12661494

申请日：2010-03-18

Applicant: Keiichi Sugimoto ,  Mitsuru Nakagawa

Inventor： Keiichi Sugimoto ,  Mitsuru Nakagawa

IPC: H01L23/28

CPC classification number: H05K3/284 ,  H05K3/281 ,  H05K5/0243 ,  H05K5/065 ,  H05K2201/09936 ,  H05K2203/1311 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146

Abstract: A method of producing an electronic device includes a holding of a circuit board and a decoration sheet in a cavity of a mold, and a filling and solidifying of thermosetting resin in the cavity. A casing is molded by the solidified thermosetting resin so as to seal electronic parts and a first face of the circuit board having the electronic parts. Further, the decoration sheet is integrated with the casing by the solidified thermosetting resin. An outer surface of the casing is defined by a second face of the circuit board opposite from the first face and the decoration sheet.

Abstract translation: 电子设备的制造方法包括在模具的空腔中保持电路板和装饰片，以及在空腔中填充和固化热固性树脂。 通过凝固的热固性树脂模制套管，以密封电子部件和具有电子部件的电路板的第一面。 此外，装饰片通过凝固的热固性树脂与壳体一体化。 壳体的外表面由电路板的与第一面和装饰片相对的第二面限定。

公开(公告)号：US08070932B2

公开(公告)日：2011-12-06

申请号：US12076425

申请日：2008-03-18

Applicant: Shih-Ping Hsu ,  Shang-Wei Chen ,  Suo-Hsia Tang ,  Chao-Wen Shih

Inventor： Shih-Ping Hsu ,  Shang-Wei Chen ,  Suo-Hsia Tang ,  Chao-Wen Shih

IPC: C25D5/02

CPC classification number: H05K1/0266 ,  H05K1/0269 ,  H05K3/107 ,  H05K3/4644 ,  H05K2201/09781 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract translation: 提出了具有可识别信息的电路板及其制造方法。 电路板内的至少一个绝缘层具有不具有电路布局的非电路区域。 在绝缘层的非电路区域中形成多个开口。 在绝缘层上形成图案化的电路层。 金属识别信息设置在非电路区域的开口中。 通过这种布置，电路板的产品状态可以通过金属图案信息进行跟踪和识别。

公开(公告)号：US20110179641A1

公开(公告)日：2011-07-28

申请号：US13056613

申请日：2009-07-31

Applicant: Kate Stone

Inventor： Kate Stone

IPC: H05K3/30 ,  B05D5/12 ,  B32B3/10

CPC classification number: B42D15/022 ,  A63F9/24 ,  A63F2011/0081 ,  B42D3/123 ,  B42D2033/46 ,  B42P2221/00 ,  B44F3/00 ,  H05K1/0266 ,  H05K3/12 ,  H05K2201/09936 ,  H05K2201/10037 ,  H05K2201/10106 ,  Y10T29/4913 ,  Y10T428/24802

Abstract: A printed article (1) comprises a substrate (2) and an image (3) printed on the substrate. The image includes line art (4) comprises conductive ink. The image includes representations of at least two items (61, 62) which overlap such that line art of a first item is joined at least one point (71) to line art of a second item.

Abstract translation: 印刷品（1）包括基板（2）和印刷在基板上的图像（3）。 图像包括线条艺术（4）包括导电油墨。 该图像包括重叠的至少两个项目（61,62）的表示，使得第一项目的线条艺术被连接到第二项目的线条艺的至少一个点（71）。

公开(公告)号：US20090205860A1

公开(公告)日：2009-08-20

申请号：US12372158

申请日：2009-02-17

Applicant: Kazutaka KOBAYASHI

Inventor： Kazutaka KOBAYASHI

IPC: H05K1/16 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0266 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/114 ,  H05K3/244 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09936 ,  Y10T29/49155 ,  H01L2924/00

Abstract: In a wiring substrate in which plural wiring layers and insulating layers are alternately stacked and the adjacent wiring layers are electrically connected through a via hole formed in the insulating layer, plural holes constructing substrate management information recognizable as a character, a symbol, etc. are formed in the outside insulating layer of the insulating layers.

Abstract translation: 在多个布线层和绝缘层交替层叠并且相邻布线层通过形成在绝缘层中的通孔电连接的布线基板中，构成可识别为字符，符号等的基板管理信息的多个孔是 形成在绝缘层的外部绝缘层中。

公开(公告)号：US07498521B2

公开(公告)日：2009-03-03

申请号：US11170823

申请日：2005-06-30

Applicant: Brian S. Forbes ,  William L. Sanderson, IV ,  Daniel J. Ragland ,  Tim Menard

Inventor： Brian S. Forbes ,  William L. Sanderson, IV ,  Daniel J. Ragland ,  Tim Menard

IPC: H05K1/03 ,  H05K3/36

CPC classification number: H05K1/0269 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0108 ,  H05K2201/09936 ,  H05K2201/10113 ,  Y10T29/49126

Abstract: A method and apparatus include providing a printed circuit board (PCB) having at least one light permeable layer, at least one non-light permeable layer having at least one void therethrough that may be vertically aligned with the at least one light permeable layer, and a source of illumination to simultaneously illuminate through the void and the at least one light permeable layer.

Abstract translation: 一种方法和装置包括提供具有至少一个透光层的印刷电路板（PCB），至少一个不透光层，其具有至少一个空隙，其可以与至少一个透光层垂直对准，以及 照明源同时照亮空隙和至少一个透光层。

公开(公告)号：US20090045367A1

公开(公告)日：2009-02-19

申请号：US12223736

申请日：2006-08-04

Applicant: Jin Young Lee ,  Gang Woon Heo ,  Young Min Yun ,  Bong Young Lee

Inventor： Jin Young Lee ,  Gang Woon Heo ,  Young Min Yun ,  Bong Young Lee

IPC: F16K31/02

CPC classification number: F15B13/0857 ,  F15B13/0839 ,  F15B13/085 ,  F15B13/0853 ,  F15B13/0875 ,  F15B13/0889 ,  F15B13/0892 ,  H05K1/0266 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/09936 ,  H05K2201/1003 ,  H05K2201/10446 ,  H05K2203/1572 ,  Y02P70/611 ,  Y10T137/87885

Abstract: A circuit board (205) for a valve block (120) of a solenoid valve manifold is described. Each valve block (120) contains a valve which is actuated by either one single solenoid or by two solenoids. Both sides (210, 220) of the circuit board (210) are provided with a circuit (212, 222). The first surface (210) of the circuit board (205) carries a single type valve circuit (212) for supplying one single solenoid with electrical energy. This first surface (210) can be mark e.g. with an “S”. The second surface (220) of the circuit board (205) carries a double-type valve circuit (222) for supplying two solenoids with electrical power. This second surface (220) can be marked e.g. with a “D”. The circuit board (205) is positioned in the respective valve block (120) with the first surface (210) or the second surface (220) facing upwards depending on whether a single- or a double-solenoid-valve is used in the respective valve block (120).

Abstract translation: 描述了用于电磁阀歧管的阀块（120）的电路板（205）。 每个阀块（120）包含由一个单个螺线管或两个螺线管致动的阀。 电路板（210）的两侧（210,220）设置有电路（212,222）。 电路板（205）的第一表面（210）承载用于向单个螺线管提供电能的单一型阀电路（212）。 该第一表面（210）可以标记为例如。 带有“S”。 电路板（205）的第二表面（220）承载用于向两个螺线管供电的双电源电路（222）。 该第二表面（220）可以被标记为例如。 带有“D”。 电路板（205）位于相应的阀块（120）中，其中第一表面（210）或第二表面（220）面向上，这取决于在相应的方法中是使用单电磁阀还是双电磁阀 阀块（120）。

公开(公告)号：US20080166497A1

公开(公告)日：2008-07-10

申请号：US12076425

申请日：2008-03-18

Applicant: Shih-Ping Hsu ,  Shang-Wei Chen ,  Suo-Hsia Tang ,  Chao-Wen Shih

Inventor： Shih-Ping Hsu ,  Shang-Wei Chen ,  Suo-Hsia Tang ,  Chao-Wen Shih

IPC: B05D5/12

CPC classification number: H05K1/0266 ,  H05K1/0269 ,  H05K3/107 ,  H05K3/4644 ,  H05K2201/09781 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract translation: 提出了具有可识别信息的电路板及其制造方法。 电路板内的至少一个绝缘层具有不具有电路布局的非电路区域。 在绝缘层的非电路区域中形成多个开口。 在绝缘层上形成图案化的电路层。 金属识别信息设置在非电路区域的开口中。 通过这种布置，电路板的产品状态可以通过金属图案信息进行跟踪和识别。