公开(公告)号：US09011181B2

公开(公告)日：2015-04-21

申请号：US14269265

申请日：2014-05-05

Applicant: Panduit Corp.

Inventor： Jack E. Caveney ,  Scott M. Lesniak

IPC: H01R13/66 ,  H05K1/02 ,  H01R13/6466 ,  H01R13/6469 ,  H01R4/24 ,  H05K1/16 ,  H01R24/64

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 网络电缆插孔包括用于平衡电感和电容耦合的印刷电路板（PCB）。 使用PCB可以形成紧凑的轨迹路径，而不会显着增加制造成本。 通过在每个迹线路径上包括两个由中性区域分开的不同的电感区域，实现了自由度的显着增益，用于设计PCB迹线图案，其中一对感应耦合区域共同抵消了由规格插头和插孔引起的感性耦合 触点，幅度和相位角。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US09000305B2

公开(公告)日：2015-04-07

申请号：US13394473

申请日：2010-09-01

Applicant: Manfred Michalk

Inventor： Manfred Michalk

IPC: H05K1/16 ,  H05K3/30 ,  G06K19/077 ,  H01Q7/00 ,  H01Q9/27 ,  H05K3/10 ,  H01L23/00 ,  H01F41/06

CPC classification number: H05K1/162 ,  G06K19/07749 ,  G06K19/07779 ,  H01F41/074 ,  H01L24/85 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01Q7/00 ,  H01Q9/27 ,  H05K3/103 ,  H05K3/30 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/1028 ,  Y10T156/10 ,  Y10T156/17 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The present invention relates to a circuit arrangement (1) having a prescribed electrical capacitance, comprising a substrate (S) having at least one metallic, electrically conductive conductor (L, Lb, Ls). According to the invention, at least one first conductor strip segment (LA1) is disposed on the substrate (S) and at least some regions of at least one second conductor strip segment (LA2, LA3, LA4) are disposed on the first conductor strip segment (LA1), wherein an electrically insulating layer (iS) is disposed between the conductor strip segments (LA1, LA2, LA3, LA4), forming a dielectric. The invention further relates to a method and a device (2) for producing a circuit arrangement (1) having a prescribed electrical capacitance.

Abstract translation: 本发明涉及具有规定电容的电路装置（1），其包括具有至少一个金属导电导体（L，Lb，Ls）的基板（S）。 根据本发明，至少一个第一导体条段（LA1）设置在基板（S）上，并且至少一个第二导体条段（LA2，LA3，LA4）的至少一些区域设置在第一导体条 （LA1），其中电绝缘层（iS）设置在导体条段（LA1，LA2，LA3，LA4）之间，形成电介质。 本发明还涉及一种用于制造具有规定电容的电路装置（1）的方法和装置（2）。

公开(公告)号：US20150041202A1

公开(公告)日：2015-02-12

申请号：US14456747

申请日：2014-08-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu AHN ,  Byoung Hwa Lee ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G17/00 ,  H01G4/06 ,  H01G4/228 ,  H01F27/24 ,  H01G4/35 ,  H01F27/29 ,  H01F27/02 ,  H01F10/00 ,  H05K1/18 ,  H01F27/33 ,  H01G4/30 ,  H01F27/28

CPC classification number: H01G17/00 ,  H01F27/2804 ,  H01F27/292 ,  H01F27/40 ,  H01F2027/2809 ,  H01G4/06 ,  H01G4/228 ,  H01G4/30 ,  H01G4/35 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/09672 ,  Y02P70/611

Abstract: A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body and connected to the conductive pattern of the inductor; an output terminal including a first output terminal formed on a second end surface of the composite body and connected to the conductive pattern of the inductor and a second output terminal disposed on a second side surface of the composite body; and a ground terminal disposed on a first side surface of the composite body and connected to the internal electrodes of the capacitor.

Abstract translation: 复合电子部件可以包括：复合体，其包括彼此耦合的电容器和电感器，所述电容器具有陶瓷体，所述陶瓷体叠置有介电层和彼此面对的电介质层的内部电极，所述电感器具有 堆叠具有导电图案的磁性层的磁性体; 输入端子，设置在复合体的第一端面上并连接到电感器的导电图案; 输出端子，包括形成在复合体的第二端面上并连接到电感器的导电图案的第一输出端子和布置在复合体的第二侧表面上的第二输出端子; 以及接地端子，其配置在复合体的第一侧面上并与电容器的内部电极连接。

公开(公告)号：US20150014039A1

公开(公告)日：2015-01-15

申请号：US14311546

申请日：2014-06-23

Applicant: NIPPON MEKTRON, LTD. ,  OSAKA UNIVERSITY

Inventor： Masaya Nogi ,  Katsuaki Suganuma ,  Hirotaka Koga ,  Natsuki Komoda ,  Hirofumi Matsumoto ,  Masayuki Iwase ,  Kazayuki Ozaki ,  Keizo Toyama

IPC: H01G4/16 ,  D21H21/14 ,  D21H11/10 ,  H05K1/18

CPC classification number: H01G4/16 ,  D21H11/10 ,  D21H21/14 ,  H01G4/203 ,  H05K1/02 ,  H05K1/0386 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/026 ,  H05K2201/09672 ,  H05K2203/178 ,  Y10T428/249921

Abstract: Disclosed are an insulating material (high-k layer) which includes a fiber assembly mainly composed of a cellulose nanofiber, and an electroconductive metal material supported by the fiber assembly; and a passive element (capacitor) which includes a high-k layer which is composed of the insulating material, and an electroconductive part stacked on the high-k layer.

Abstract translation: 公开了一种绝缘材料（高k层），其包括主要由纤维素纳米纤维构成的纤维集合体和由纤维集合体支撑的导电金属材料; 以及包括由绝缘材料构成的高k层的无源元件（电容器）和堆叠在高k层上的导电部分。

公开(公告)号：US20140361437A1

公开(公告)日：2014-12-11

申请号：US14082289

申请日：2013-11-18

Applicant: SK hynix Inc.

Inventor： Hyun Chul SEO ,  Jong Hoon KIM ,  Jae Woong YU

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/4846 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of the ridge portions. Related methods are also provided.

Abstract translation: 提供封装衬底。 封装衬底包括芯层，其具有第一表面，第一表面限定沟槽部分和沟槽部分之间的脊部分，每个沟槽部分的底表面上的至少一个第一迹线以及脊部的各个顶表面上的第二迹线 部分。 还提供了相关方法。

公开(公告)号：US20140306793A1

公开(公告)日：2014-10-16

申请号：US14237981

申请日：2012-08-15

Applicant: King Abdullah University of Science and Technology

Inventor： Atif Shamim ,  Eyad Arabi

IPC: H01F27/28

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F2017/0026 ,  H01F2017/0073 ,  H03H7/0115 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1775 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4644 ,  H05K2201/0141 ,  H05K2201/09254 ,  H05K2201/09672 ,  H05K2201/09809

Abstract: Various methods and systems are provided for high Q, miniaturized LCP-based passive components. In one embodiment, among others, a spiral inductor includes a center connection and a plurality of inductors formed on a liquid crystal polymer (LCP) layer, the plurality of inductors concentrically spiraling out from the center connection. In another embodiment, a vertically intertwined inductor includes first and second inductors including a first section disposed on a side of the LCP layer forming a fraction of a turn and a second section disposed on another side of the LCP layer. At least a portion of the first section of the first inductor is substantially aligned with at least a portion of the second section of the second inductor and at least a portion of the first section of the second inductor is substantially aligned with at least a portion of the second section of the first inductor.

Abstract translation: 提供了高Q，小型化的基于LCP的无源​​组件的各种方法和系统。 在一个实施例中，螺旋电感器包括中心连接和形成在液晶聚合物（LCP）层上的多个电感器，多个电感器从中心连接同心地向外螺旋出。 在另一个实施例中，垂直交织的电感器包括第一和第二电感器，该电感器包括设置在LCP层的一侧的第一部分，其形成一小部分转弯，而第二部分设置在LCP层的另一侧上。 第一电感器的第一部分的至少一部分基本上与第二电感器的第二部分的至少一部分对准，并且第二电感器的第一部分的至少一部分基本上对准至少部分 第一电感的第二部分。

公开(公告)号：US20140305686A1

公开(公告)日：2014-10-16

申请号：US14246266

申请日：2014-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi KITAJIMA

IPC: H05K1/18

CPC classification number: H05K1/0298 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/341 ,  H05K3/4629 ,  H05K2201/0352 ,  H05K2201/09045 ,  H05K2201/09672

Abstract: A multilayer wiring substrate includes a multilayer body in which a plurality of insulating layers is stacked and to which an electronic component is mounted, a plurality of connection terminals disposed on one principal surface of the multilayer body for connection to the electronic component, and a plurality of rear electrodes disposed on the other principal surface of the multilayer body, wherein the connection terminals are each arranged in overlapped relation to one of the rear electrodes when looked at in a plan view of the multilayer wiring substrate.

Abstract translation: 多层布线基板包括堆叠多个绝缘层并且安装电子部件的多层体，设置在多层体的一个主面上的多个连接端子，用于与电子部件连接，多个连接端子 设置在所述多层体的另一主面上的后电极，其中，当在所述多层布线基板的俯视图中观察时，所述连接端子与所述后电极中的一个重叠地布置。

公开(公告)号：US20140242851A1

公开(公告)日：2014-08-28

申请号：US14101736

申请日：2013-12-10

Applicant: ADC GmbH

Inventor： David Patrick Murray ,  Bernard Harold Hammond, JR.

IPC: H01R13/6461

CPC classification number: H01R13/6466 ,  H01R13/6461 ,  H01R13/6464 ,  H01R13/6658 ,  H01R13/6691 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/53209

Abstract: Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling.

Abstract translation: 公开了一种用于在千斤顶中提供串扰补偿的方法和系统。 根据一种方法，串扰补偿适于补偿位于插入插座内的插头处的电容耦合处产生的不期望的串扰。 该方法包括将第一时间延迟定位成离开插头的电容耦合的第一电容耦合，与插头的电容耦合相比，第一电容耦合具有更大的幅度和相反的极性。 该方法还包括在第一时间延迟从第一电容耦合定位第二电容耦合，第二时间延迟对应于优化近端串扰的平均时间延迟。 第二电容耦合具有与第一电容耦合相比具有相同的总体幅度但具有相反的极性，并且包括以与第一电容耦合不同的时间延迟隔开的两个电容元件。

公开(公告)号：US08813000B2

公开(公告)日：2014-08-19

申请号：US14042908

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US20140197902A1

公开(公告)日：2014-07-17

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。