公开(公告)号：US20020025724A1

公开(公告)日：2002-02-28

申请号：US09409530

申请日：1999-09-30

Inventor： YAKOV BELOPOLSKY ,  JOHN R. ELLIS

IPC: H05K001/00

CPC classification number: H01R13/6463 ,  H01R12/7082 ,  H01R12/7088 ,  H01R13/658 ,  H05K1/148 ,  H05K2201/0792 ,  H05K2201/097 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2203/1572 ,  Y10S439/941

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacitance. The connector for connecting circuit boards comprises a first contact having a first mating portion and a second mating portion, and a second contact having a first mating portion and a second mating portion, wherein the first and second contacts are interleaved.

Abstract translation: 提供了用于降低电导体中的电感的低电感电源连接器。 接口连接器将电路板连接在一起，同时减少电感和增加载流电容。 用于连接电路板的连接器包括具有第一配合部分和第二配合部分的第一接触件和具有第一配合部分和第二配合部分的第二接触件，其中第一和第二接触件被交错。

公开(公告)号：US06223419B1

公开(公告)日：2001-05-01

申请号：US09243159

申请日：1999-02-02

Applicant: Igor Abramov

Inventor： Igor Abramov

IPC: H01F4102

CPC classification number: H01F27/292 ,  H01F17/0033 ,  H05K1/0233 ,  H05K3/3442 ,  H05K2201/0792 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10583 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4902

Abstract: A monolithic inductor (10) comprises an elongated substrate having opposite distal ends (14) and (16), each end having an end cap extending from the opposite ends to support the substrate (12) in spaced relation from a PC board, the end caps being formed with non-mounting areas and a deflection area for preventing the substrate resting on the non-mounting area, a substantially steep side wall (16) on the substrate side of the end cap (14) at the non-mounting area, and an inclined ramp extending up to a top of the end cap on the substrate side substantially opposite the non-mounting area, an electrically conductive soldering band (30) extending partially around each end cap, each soldering band having a gap (34) at the non-mounting area for thereby reducing parasitic conduction in the band (30), and an electrically conductive layer formed on the substrate in a helical path extending between the opposite ends and in electrical contact with the conductive soldering bands (30) at the ramps (120).

Abstract translation: 单片电感器（10）包括具有相对的远端（14）和（16）的细长衬底，每个端部具有从相对端延伸的端盖，以与PC板隔开的关系支撑衬底（12），端部 盖子形成有非安装区域和用于防止基板搁置在非安装区域上的偏转区域，在非安装区域处在端盖（14）的基板侧上的基本上陡峭的侧壁（16） 以及一个倾斜的斜坡，其基本上与所述非安装区域相对地延伸到所述端盖的顶部的顶部;导电焊接带（30），其部分地围绕每个端盖延伸，每个焊带具有间隙（34） 所述非安装区域由此减小所述带（30）中的寄生传导，以及形成在所述基板上的螺旋形路径中的导电层，所述导电层在所述相对端之间延伸并在所述斜面处与所述导电焊带（30）电接触 （120）。

公开(公告)号：US6024589A

公开(公告)日：2000-02-15

申请号：US856500

申请日：1997-05-14

Applicant: John W. Hahn, IV ,  James K. Koch

Inventor： John W. Hahn, IV ,  James K. Koch

IPC: H01R4/30 ,  H01R12/52 ,  H05K1/14 ,  H05K3/32 ,  H01R4/60

CPC classification number: H01R12/52 ,  H05K1/148 ,  H01R4/30 ,  H05K2201/0792 ,  H05K2201/10272 ,  H05K2201/10409 ,  H05K2203/1572 ,  H05K3/325

Abstract: The present invention provides a reliable high current connector for connecting the ground and power planes of a first PCB to the ground and power planes of a second PCB. The power bus bar is comprised of a first conductive structure having a first and second surface, a second conductive structure having a first and second, and an inner insulative structure positioned between the first surface of the first conductive structure and the first surface of the second conductive structure. A fastening means, inserted through openings in the conductive structures, provides a secure, low resistance electrical connection from the first or second conductive structure of the bus bar to the electrical traces of the PCB. The high dielectric constant of the insulator provides distributed capacitance between the first conductive structure and the second conductive structure, lowering the AC impedance. The bus bar design mounts both above and below each PCB and increases mechanical strength and spatial efficiency compared to previous bus bar designs.

Abstract translation: 本发明提供了一种可靠的大电流连接器，用于将第一PCB的接地层和电源平面连接到第二PCB的接地层和电源层。 电源母线由具有第一和第二表面的第一导电结构组成，具有第一和第二导电结构的第二导电结构和位于第一导电结构的第一表面和第二导电结构的第一表面之间的内部绝缘结构 导电结构。 通过导电结构中的开口插入的紧固装置提供从母线的第一或第二导电结构到PCB的电迹线的牢固的低电阻电连接。 绝缘体的高介电常数在第一导电结构和第二导电结构之间提供分布电容，降低了交流阻抗。 汇流条设计安装在每个PCB的上方和下方，与以前的母线设计相比，增加了机械强度和空间效率。

公开(公告)号：US6020562A

公开(公告)日：2000-02-01

申请号：US967489

申请日：1997-11-11

Applicant: Lawrence M. Burns ,  Nicholas Mitchell ,  Theresa Bradshaw ,  Chong Woo

Inventor： Lawrence M. Burns ,  Nicholas Mitchell ,  Theresa Bradshaw ,  Chong Woo

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H01R9/09 ,  H01R23/68

CPC classification number: H05K1/0216 ,  H05K1/111 ,  H05K1/0231 ,  H05K1/0243 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/0969 ,  H05K2201/1006 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K3/3421 ,  Y02P70/611

Abstract: Component mounting pads for multi-layer printed circuit boards encompass a smaller area than conventional pads, reducing parasitic capacitance between the pads and a ground plane layer. A number of such pads are arranged to accommodate standard surface-mount component sizes and packages. Further capacitance reductions are achieved by implementing mesh areas or apertures in the board's ground plane opposite the reduced-capacitance pads.

Abstract translation: 用于多层印刷电路板的组件安装垫包括比传统焊盘更小的面积，减小焊盘和接地平面层之间的寄生电容。 许多这样的垫布置成适应标准的表面贴装部件尺寸和包装。 通过在电路板的接地平面中与减小电容的焊盘相对地实现网格区域或孔径来实现进一步的电容减小。

公开(公告)号：US5751555A

公开(公告)日：1998-05-12

申请号：US697095

申请日：1996-08-19

Applicant: Henry L. Pfizenmayer ,  Frederick C. Wernett, III

Inventor： Henry L. Pfizenmayer ,  Frederick C. Wernett, III

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K1/16

CPC classification number: H05K1/141 ,  H05K1/0216 ,  H05K1/145 ,  H05K2201/0792 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/368

Abstract: An electronic component with reduced capacitance includes a substrate (12) with an interconnect line (14), an additional substrate (11) with an interconnect line (13) wherein the substrate (12) overlies the additional substrate (11), an electronic device (15) overlying the substrate (12) and electrically coupled to the interconnect line (14) of the substrate (12), and an additional electronic device (17) having a lead (23) and an additional lead (26) wherein the lead (23) overlies the substrate (12) and is electrically coupled to the interconnect line (14) of the substrate (12) and wherein the additional lead (26) overlies the additional substrate (11) and is electrically coupled to the interconnect line (13) of the additional substrate (11).

Abstract translation: 具有减小的电容的电子部件包括具有互连线（14）的衬底（12），具有互连线（13）的附加衬底（11），其中衬底（12）覆盖附加衬底（11），电子器件 （15）覆盖在衬底（12）上并电耦合到衬底（12）的互连线（14），以及附加电子器件（17），其具有引线（23）和附加引线（26），其中引线 （23）覆盖在衬底（12）上并且电耦合到衬底（12）的互连线（14），并且其中附加引线（26）覆盖附加衬底（11）并且电耦合到互连线 13）。

公开(公告)号：US5736784A

公开(公告)日：1998-04-07

申请号：US740595

申请日：1996-10-31

Applicant: Lewis R. Dove

Inventor： Lewis R. Dove

IPC: H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/45 ,  H05K1/0243 ,  H05K3/3426 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/45013 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01031 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/141 ,  H05K2201/0792 ,  H05K2201/09727 ,  H05K2201/1034 ,  H05K2201/10818 ,  Y02P70/613

Abstract: A variable-width lead interconnection structure disposed between a printed circuit board and a multichip module is presented. An edge clip with leads having a widened middle section is provided to optimize manufacturability and electrical performance. Each lead has a characteristic width and spacing of conventional leads where the leads are soldered to a multichip module or PCB. However, in between each end, each lead has a middle section that is widened to provide a characteristic impedance closer to the ideal 50 ohms, thus producing structures with better return loss at high frequencies.

Abstract translation: 提出了布置在印刷电路板和多芯片模块之间的可变宽度引线互连结构。 提供具有加宽中间部分的引线的边缘夹以优化可制造性和电性能。 每个引线具有传统引线的特征宽度和间距，其中引线焊接到多芯片模块或PCB。 然而，在每个端部之间，每个引线具有被加宽的中间部分，以提供更接近理想的50欧姆的特征阻抗，从而产生在高频下具有更好的回波损耗的结构。

公开(公告)号：US5379189A

公开(公告)日：1995-01-03

申请号：US143901

申请日：1993-11-02

Applicant: Terence C. Merriman

Inventor： Terence C. Merriman

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K7/02

CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/09663 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electrical circuit has a substrate and a surface mount capacitor having a connector pad at each end. The substrate has two separate contact pads that are both soldered to the same connector pad on the capacitor. Two further contact pads on the substrate are soldered to the other connector pad on the capacitor. The contact pads on the substrate are connected to tracks that extend to plated-through holes and are electrically connected to one another at a point remote from the capacitor.

Abstract translation: 电路具有基板和表面贴装电容器，每个端部具有连接器焊盘。 衬底具有两个单独的接触焊盘，两个焊盘焊接到电容器上的相同连接器焊盘。 衬底上的另外两个接触焊盘焊接到电容器上的另一个连接器焊盘。 衬底上的接触焊盘连接到延伸到电镀通孔的轨道，并且在远离电容器的点处彼此电连接。

公开(公告)号：US5375035A

公开(公告)日：1994-12-20

申请号：US35393

申请日：1993-03-22

Applicant: D. Joe Stoddard

Inventor： D. Joe Stoddard

IPC: H01G2/06 ,  H01G4/252 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01G1/035

CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  H05K3/0094 ,  Y02P70/611 ,  Y02P70/613

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract translation: 一种用于印刷电路板的电容器安装结构，其中电容器包括连接到印刷电路板中的第一和第二导体平面的第一和第二端子。 三个通孔安装在印刷电路板中与电容器中间对准的位置。 第一导体焊盘安装在电容器的一端下方，并且包括电连接到第一和第三通孔的间隔开的延伸部分。 第二导体焊盘安装在电容器的另一端下方，并且包括连接到第二或中间通孔的中心延伸部分。 以这种方式，可用于产生寄生电感的区域被最小化，从而提高了电容器的工作效率。