公开(公告)号：US07084351B2

公开(公告)日：2006-08-01

申请号：US10237645

申请日：2002-09-09

Applicant: Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

IPC: H05K1/18

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

公开(公告)号：US07076868B2

公开(公告)日：2006-07-18

申请号：US10819220

申请日：2004-04-07

Applicant: Yutaka Kaneda

Inventor： Yutaka Kaneda

IPC: H01R9/00

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 μm are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 μm, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.

Abstract translation: 公开了一种制造具有凸块的布线电路板的方法，其中可以进行稳定的凸起连接，并且不需要复杂的操作，例如电镀预处理。 通过在金属箔的凸块形成表面上形成用于凸块形成表面的蚀刻掩模，形成具有0.2至20μm的表面粗糙度的尖端表面的凸起，该蚀刻掩模的厚度（t 1 + t 2）为 布线电路的厚度t 1和在布线电路上形成的凸点的高度t 2，其凸起形成表面的表面粗糙度为0.2至20μm，并且从蚀刻侧蚀刻金属箔 用于凸块形成的掩模到与期望的凸块高度t 2相对应的深度。

公开(公告)号：US20060145313A1

公开(公告)日：2006-07-06

申请号：US11320616

申请日：2005-12-30

Applicant: Kwan Lee

Inventor： Kwan Lee

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L21/565 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/184 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/09981 ,  H05K2201/10727 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package device including a lead frame including a die pad to which a semiconductor chip is attached and a plurality of terminals for electrical interconnection of the semiconductor chip to an external device. The device also includes a plurality of bonding wires for electrically interconnecting the terminals to the semiconductor chip, a package body for protecting the semiconductor chip, die pad, terminals, and bonding wires, and a plurality of connections bonded to the terminals for electrically interconnecting the semiconductor chip to the external device. The plurality of connections are made of solder balls or bumps and electrically interconnected to board connectors of an external circuit board.

Abstract translation: 一种半导体封装器件，包括引线框架，该引线框架包括安装有半导体芯片的管芯焊盘和用于将半导体芯片电连接到外部设备的多个端子。 该装置还包括用于将端子与半导体芯片电连接的多个接合线，用于保护半导体芯片，管芯焊盘，端子和接合线的封装主体，以及接合到端子的多个连接件，用于将 半导体芯片到外部器件。 多个连接由焊球或凸块制成，并且电连接到外部电路板的板连接器。

公开(公告)号：US20060139410A1

公开(公告)日：2006-06-29

申请号：US11358203

申请日：2006-02-22

Applicant: Shogo Kawamura ,  Toshihiro Mori ,  Hisashi Fukai ,  Naoki Nakajo

Inventor： Shogo Kawamura ,  Toshihiro Mori ,  Hisashi Fukai ,  Naoki Nakajo

IPC: B41J2/05

CPC classification number: H05K3/361 ,  B41J2/14024 ,  B41J2/14072 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0397 ,  H05K2201/10977

Abstract: A liquid discharge recording head includes a recording element with a discharge port for discharging liquid and an electrically connecting portion arranged adjacent to the discharge port and receiving an electric signal for controlling the discharge of the discharge port. The liquid discharge recording head further includes a flexible wiring substrate for covering at least a portion of the recording element. The flexible wiring substrate includes each of a device hole for exposing the discharge port and a bonding hole arranged facing the electrically connecting portion independently. The liquid discharge recording head further includes a sealing agent for covering at least a portion of the electrically connecting portion and filled to at least a portion of the bonding hole. Thus, a liquid discharge recording head that enhances recording performance and that has superior productivity while maintaining reliability of the recording performance is provided.

公开(公告)号：US07067912B2

公开(公告)日：2006-06-27

申请号：US10860493

申请日：2004-06-04

Applicant: Yoshihiko Takeuchi ,  Yasuhito Ohwaki ,  Yuichi Takayoshi

Inventor： Yoshihiko Takeuchi ,  Yasuhito Ohwaki ,  Yuichi Takayoshi

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/04 ,  H05K1/03

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/141 ,  H05K1/147 ,  H05K3/108 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/0969 ,  H01L2924/00

Abstract: A wired circuit board can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signals. The wired circuit board includes a relay flexible wiring circuit board formed by a first wired circuit board including a first metal substrate, a first insulating base layer, a first conductor layer and a first insulating cover layer which is substantially identical in layer structure with the suspension board with circuit and a second wired circuit board connected with the first wired circuit board for connecting with a control circuit board. Since the suspension board with circuit and the first wired circuit board are rendered substantially identical in layer structure, both characteristic impedances at these connection points can be matched.

Abstract translation: 布线电路板可以通过简单的结构来控制悬挂板的导线之间的连接点处的特性阻抗，其电路和与其连接的布线电路板的端子部分，以便即使对于细间距布线或高频信号来提高信号传输效率。 布线电路板包括由第一布线电路板形成的中继柔性布线电路板，第一布线电路板包括第一金属基板，第一绝缘基底层，第一导体层和第一绝缘覆盖层，其与悬浮液的层结构基本相同 与第一布线电路板连接的第二布线电路板用于与控制电路板连接。 由于具有电路的悬架板和第一布线电路板的层结构基本相同，所以这些连接点的两个特性阻抗都可以匹配。

公开(公告)号：US20060131730A1

公开(公告)日：2006-06-22

申请号：US11304868

申请日：2005-12-14

Applicant: Junichi Nakamura

Inventor： Junichi Nakamura

IPC: H01L23/12

CPC classification number: H05K3/4007 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15159 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2203/1536 ,  H01L2224/05552

Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring (24), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).

Abstract translation: 公开了一种半导体封装及其制造方法，通过使用包含较少量的引线的外部连接端子或半导体元件安装端子，同时实现端子的精细间距来解决环境问题。 半导体封装包括：多个绝缘树脂层的基板（20），形成在基板的最上表面上的半导体元件安装端子（18）和形成在其底面上的外部连接端子（12）。 每个外部连接端子（12）形成为从封装的底表面向下突出的凸起，并且每个凸起都填充有绝缘树脂（14），同时其表面被金属（16）覆盖。 包括导体通孔（26a）的布线（24），（26）将金属层16的金属与半导体元件安装端子（18）电连接。

公开(公告)号：US20060124351A1

公开(公告)日：2006-06-15

申请号：US11350032

申请日：2006-02-09

Applicant: Hidetoshi Kusano ,  Shinji Kumon

Inventor： Hidetoshi Kusano ,  Shinji Kumon

IPC: H01R12/04 ,  H05K1/11 ,  H01K3/10

CPC classification number: H05K3/4652 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2203/0376 ,  H05K2203/0733 ,  H05K2203/1383 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Metal foil is laminated via an insulating layer so as to cover the first layer circuit wiring formed on a conductive substrate, and a resist layer is formed so as to cover the second layer circuit wiring formed by pattern-etching the metal foil. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, in interlayer via holes each formed by applying a laser beam to the resist layer, thereby to establish interlayer connection between the first layer circuit wiring and the second layer circuit wiring. Subsequently, the resist layer is removed, and then, using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, in hole portions of an insulating layer formed so as to cover the second layer circuit wiring, thereby to form external connection terminals. Then, the conductive substrate is removed entirely or partly to expose the first layer circuit wiring, thereby to manufacture a flexible multilayer wiring board.

公开(公告)号：US07059868B1

公开(公告)日：2006-06-13

申请号：US10378268

申请日：2003-03-03

Applicant: Yan Yan

Inventor： Yan Yan

IPC: H01R12/00

CPC classification number: H05K3/365 ,  G11B5/4846 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/167

Abstract: A system and method for connecting flexible circuitry in a disk drive system such as that used in computer systems. The system and method allow a large number of traces to be connected in a small area by forming male and female connector portions at an end of a mating pair of traces. the male and female portions are formed using conventional flexible circuit fabrication techniques, making possible very accurate control of very small built-in type connectors. The connection can be uncoupled and re-coupled, and added security of attachment can be achieved through the use of ultra-sonic bonding and use of a mechanical clamp.

Abstract translation: 用于连接诸如在计算机系统中使用的磁盘驱动器系统中的柔性电路的系统和方法。 该系统和方法允许通过在匹配的一对迹线的端部处形成阳和阴连接器部分而将大量迹线连接在小的区域中。 使用传统的柔性电路制造技术形成阳和阴部分，使得可以非常精确地控制非常小的内置型连接器。 连接可以分离和重新耦合，并且可以通过使用超声波键合和使用机械夹具来实现附加的附加安全性。

公开(公告)号：US20060118830A1

公开(公告)日：2006-06-08

申请号：US11326140

申请日：2006-01-05

Applicant: Dennis Brunner ,  David Buster ,  Michael Graff ,  Daniel Luebbert ,  Nathan Kreutter ,  Rui Yang

Inventor： Dennis Brunner ,  David Buster ,  Michael Graff ,  Daniel Luebbert ,  Nathan Kreutter ,  Rui Yang

IPC: H01L29/768

CPC classification number: H01L24/10 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/002 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/0369 ,  H01L2924/00

Abstract: Provided are partially etched dielectric films with raised conductive features. Also provided are methods for forming the raised conductive features in the dielectric films, which methods include partially etching the dielectric films.

Abstract translation: 提供了具有凸起导电特征的部分蚀刻的电介质膜。 还提供了用于在介电膜中形成凸起的导电特征的方法，该方法包括部分蚀刻介电膜。

公开(公告)号：US20060113654A1

公开(公告)日：2006-06-01

申请号：US11328316

申请日：2006-01-10

Applicant: Joseph Sun ,  Kuang-Chih Cheng ,  Ming-Chieh Chen

Inventor： Joseph Sun ,  Kuang-Chih Cheng ,  Ming-Chieh Chen

IPC: H01L23/02

CPC classification number: H01L27/14618 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0367 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.

Abstract translation: 提供具有柔性布线基板的半导体器件的封装及其方法。 该半导体器件的封装包括：半导体衬底，其表面上具有至少一个衬垫，与焊盘接合的凸块，凸块上的粘合剂层;以及柔性布线衬底，具有至少一个接触部分与 由粘合剂层撞击。 本发明使柔性布线基板直接导电地附着在半导体基板上。 包装尺寸缩小，可以降低成本。