公开(公告)号：US07304249B2

公开(公告)日：2007-12-04

申请号：US10837701

申请日：2004-05-04

Applicant: Sung-Gue Lee ,  Yong-Il Kim

Inventor： Sung-Gue Lee ,  Yong-Il Kim

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/243 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/0597 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: Bonding pad(s) for a printed circuit board with circuit patterns are provided. The bonding pad(s) include a plurality of copper patterns formed on the PCB and electrically connected to the circuit patterns, a filler filled between the copper patterns such that an upper surface of the copper pattern is exposed, and a plating layer applied at an upper surface of the copper patterns. An interval between wire bonding pad(s) is reduced by preventing a nickel plating layer and a gold plating layer from protruding at a lower portion of a copper pattern when they are formed on the copper patterns.

Abstract translation: 提供了具有电路图案的印刷电路板的接合焊盘。 焊盘包括形成在PCB上并电连接到电路图案的多个铜图案，填充在铜图案之间的填充物，使得铜图案的上表面暴露，并且镀覆层 铜图案的上表面。 通过防止镀镍层和镀金层在铜图案上形成时在铜图案的下部突出，从而降低引线接合焊盘之间的间隔。

公开(公告)号：US07303984B2

公开(公告)日：2007-12-04

申请号：US11081527

申请日：2005-03-17

Applicant: Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

Inventor： Bily Wang ,  Jonnie Chuang ,  Hui-Yen Huang

IPC: H01L21/4763

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/0052 ,  H05K2201/09881 ,  H05K2203/0228 ,  H05K2203/0278 ,  H05K2203/1536

Abstract: A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite material into the trench, polishing a surface of the substrate and forming a covering material on the surface of the substrate. Therefore, the method is provided for combining the polymer composite material into the substrate, thereby to raise cutting precision and strength of the semiconductor substrate structure.

Abstract translation: 半导体衬底结构包括其上形成有沟槽的衬底，提供到沟槽中的聚合物复合材料和形成在衬底上的电镀导电层。 此外，半导体衬底处理方法包括以下步骤：提供在其上形成沟槽的衬底，将聚合物复合材料供应到沟槽中，抛光衬底的表面并在衬底的表面上形成覆盖材料。 因此，提供了将聚合物复合材料组合到基板中的方法，从而提高半导体基板结构的切割精度和强度。

公开(公告)号：US20070209202A1

公开(公告)日：2007-09-13

申请号：US10599901

申请日：2005-03-02

Applicant: Georg Busch

Inventor： Georg Busch

IPC: H05K3/02 ,  H01B13/00

CPC classification number: H05K3/4626 ,  H05K1/095 ,  H05K3/0052 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0759 ,  H05K2203/162 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for producing printed circuit boards and/or corresponding constructs that includes points where through-connections are created. The method vitiates the need for a very complex brushing process by using low cost lacquer variants. Moreover, the disclosed methods allow additional strip conductors or appropriate layers to be guided directly across the through connections rather than just to the through connections.

Abstract translation: 一种用于生产印刷电路板和/或相应结构的方法，其包括产生贯通连接的点。 该方法通过使用低成本的漆变体来消除对非常复杂的刷洗过程的需要。 此外，所公开的方法允许额外的带状导体或适当的层被直接引导穿过贯穿连接，而不仅仅是直通连接。

公开(公告)号：US07232496B2

公开(公告)日：2007-06-19

申请号：US11068781

申请日：2005-03-02

Applicant: Masayuki Yoshida ,  Shunji Aoki ,  Junichi Sutoh ,  Genichi Watanabe

Inventor： Masayuki Yoshida ,  Shunji Aoki ,  Junichi Sutoh ,  Genichi Watanabe

IPC: B32B37/00 ,  B32B38/00 ,  H01F41/00 ,  H01G13/00

CPC classification number: H05K3/4667 ,  C04B35/6269 ,  H01G4/30 ,  H05K1/0306 ,  H05K3/0023 ,  H05K2201/09881 ,  H05K2203/0514

Abstract: The present invention provides a method for manufacturing an electronic part that can cope with downsizing, improvement in performance and quality of a multilayer electronic part. A ceramic green sheet is produced by forming on a substrate or on a layer formed on a substrate an internal electrode having a predetermined thickness by a discretional process, forming a photosensitive ceramic slurry on a surface of the substrate or the layer and the internal electrode in such a way that its thickness just before exposure will be substantially equal to or smaller than the thickness of the internal electrode from the surface of the substrate or the layer, irradiating the photosensitive ceramic slurry with light from the upper side of the substrate to perform exposure while masking the internal electrode pattern, to selectively harden the surface of the photosensitive ceramic slurry, the exposure amount being controlled in such a way that the surface of the photosensitive ceramic slurry is hardened, and removing the portion of the photosensitive ceramic slurry that has not been exposed by a development process to expose a surface of the internal electrode pattern.

Abstract translation: 本发明提供一种能够应对小型化，提高多层电子部件的性能和质量的电子部件的制造方法。 通过在基板上或在基板上形成具有预定厚度的内部电极的层来形成陶瓷生片，在基板或层和内部电极的表面上形成感光陶瓷浆料 使其刚刚曝光之前的厚度将基本上等于或小于从基板或层的表面的内部电极的厚度，用来自基板的上侧的光照射感光陶瓷浆料以进行曝光 同时掩蔽内部电极图案，以选择性地硬化感光陶瓷浆料的表面，曝光量被控制为使得感光陶瓷浆料的表面硬化，并且去除不具有感光陶瓷浆料的部分感光陶瓷浆料 通过显影处理曝光以暴露内部电极图案的表面。

公开(公告)号：US20070102191A1

公开(公告)日：2007-05-10

申请号：US11644143

申请日：2006-12-22

Applicant: Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

Inventor： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

IPC: H05K1/11

CPC classification number: H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

Abstract translation: 本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且 多层布线基板。 形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。 在第二布线基板的层叠之后，最后蚀刻并去除支撑片。 第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。

公开(公告)号：US20070085217A1

公开(公告)日：2007-04-19

申请号：US11542871

申请日：2006-10-04

Applicant: Haruo Sorimachi

Inventor： Haruo Sorimachi

IPC: H01L23/48

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49861 ,  H01L24/27 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: A mounting board on which a semiconductor chip having multiple connection bumps is to be mounted by flip-chip bonding is disclosed. The mounting board includes multiple connection pads to be electrically connected to the corresponding connection bumps, where the connection pads have respective surfaces coated with solder; and an insulating layer configured to surround the connection pads and isolate the connection pads from each other. Each of the connection pads has a first region and at least one second region to be connected to a corresponding one of the connection bumps. The first region has a surface substantially as high as a surface of the insulating layer and the second region has a surface lower than the surface of the first region.

Abstract translation: 公开了一种通过倒装芯片接合来安装具有多个连接凸块的半导体芯片的安装板。 安装板包括多个连接焊盘以与相应的连接凸块电连接，其中连接焊盘具有涂覆有焊料的相应表面; 以及绝缘层，其被配置为围绕连接焊盘并将连接焊盘彼此隔离。 每个连接焊盘具有第一区域和至少一个第二区域，以连接到对应的一个连接凸块。 第一区域具有与绝缘层的表面大致相同的表面，并且第二区域具有比第一区域的表面低的表面。

公开(公告)号：US20070080439A1

公开(公告)日：2007-04-12

申请号：US11542261

申请日：2006-10-04

Applicant: Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

Inventor： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract translation: 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US20070069984A1

公开(公告)日：2007-03-29

申请号：US11528186

申请日：2006-09-26

Applicant: Chul-Hong Kim ,  Jin-Keun Jung

Inventor： Chul-Hong Kim ,  Jin-Keun Jung

IPC: G09G3/28

CPC classification number: H05K3/323 ,  H01J2211/46 ,  H01R4/04 ,  H01R12/62 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/09881 ,  H05K2203/1189

Abstract: The present invention relates to a plasma display panel which includes a plasma display panel, a driving circuit for driving the plasma display panel, an electrical signal transmitting wire for electrically connecting an electrode extended from the plasma display panel to the driving circuit, and an adhesive film interposed between the terminal end of the electrical signal transmitting wire and the terminal end of the electrode of the plasma display panel and electrically connecting between terminal ends. The adhesive film includes an anisotropic conductive film layer having a plurality of conductive particles and an insulated dummy at either or both ends of the anisotropic conductive film layer. Alternatively, the adhesive film may include a plurality of conductive particles with an insulated layer on each side.

Abstract translation: 等离子体显示面板技术领域本发明涉及等离子体显示面板，其包括等离子体显示面板，用于驱动等离子体显示面板的驱动电路，用于将从等离子体显示面板延伸的电极电连接到驱动电路的电信号传输线，以及粘合剂 插入在电信号传输线的终端和等离子体显示面板的电极的终端之间并且电连接在终端之间的膜。 粘合膜包括在各向异性导电膜层的两端或两端具有多个导电粒子和绝缘假人的各向异性导电膜层。 或者，粘合膜可以包括在每一侧上具有绝缘层的多个导电颗粒。

公开(公告)号：US20070068699A1

公开(公告)日：2007-03-29

申请号：US11236960

申请日：2005-09-28

Applicant: Ernest Lentschke ,  Jeffrey Hailey ,  Raymond McCormick

Inventor： Ernest Lentschke ,  Jeffrey Hailey ,  Raymond McCormick

IPC: H05K1/16 ,  H05K1/03

CPC classification number: H05K1/0231 ,  H05K1/0227 ,  H05K1/162 ,  H05K2201/0209 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09881 ,  Y10T29/4913

Abstract: An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.

Abstract translation: 信息处理系统具有印刷电路板，其具有分割电源平面，具有多个部分，该多个部分可用于将印刷电路板的单个导电箔层上的不同电压分配到印刷电路板上的组件。 分开的功率平面部分的电容耦合可以通过部分之间的高电介质填充来增强。

公开(公告)号：US07172925B2

公开(公告)日：2007-02-06

申请号：US10537994

申请日：2002-12-12

Applicant: Keiichi Murakami

Inventor： Keiichi Murakami

IPC: H01L21/00 ,  H05K7/02 ,  B05D5/12

CPC classification number: H05K3/281 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/09881 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0537 ,  H05K2203/066 ,  H05K2203/085 ,  H05K2203/1152 ,  H05K2203/1536 ,  H01L2924/00

Abstract: There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring board with circuit patterns formed thereon; placing the laminated plural sets of the laminated bodies interposed between a pair of smoothing plates and collectively pressing the laminated bodies in a reduced pressure atmosphere used for curing the resin; and then polishing the cured resin covering the circuit patterns, thereby exposing the circuit patterns.

Abstract translation: 提供一种制造平板印刷线路板的方法，其中电路图案之间的空间用树脂填充。 该方法包括：通过脱模膜层叠多个层叠体，通过将半固化树脂片叠置在其上形成有电路图案的印刷线路板上形成; 将层叠的多组层叠体置于一对平滑板之间，并在用于固化树脂的减压气氛中一起挤压层叠体; 然后对覆盖电路图案的固化树脂进行抛光，从而露出电路图案。