公开(公告)号：US11869834B2

公开(公告)日：2024-01-09

申请号：US17314187

申请日：2021-05-07

Applicant: TDK CORPORATION

Inventor： Takashi Daitoku ,  Susumu Taniguchi ,  Akiko Seki ,  Atsushi Sato ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hisayuki Abe

IPC: H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H01L21/48 ,  H05K3/40 ,  G06F3/044

CPC classification number: H01L23/49838 ,  G06F3/044 ,  H01L21/4857 ,  H01L23/49866 ,  H01L33/62 ,  H05K1/09 ,  H05K3/4007 ,  H01L2933/0066 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/04

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

公开(公告)号：US20230371187A1

公开(公告)日：2023-11-16

申请号：US18315735

申请日：2023-05-11

Applicant: AMAZING COOL TECHNOLOGY CORPORATION

Inventor： Shiann-Tsong TSAI ,  Yang-Ming SHIH ,  Hung-Yun HSU

IPC: H05K3/38 ,  H05K1/09

CPC classification number: H05K3/388 ,  H05K1/092 ,  H05K2201/0323 ,  H05K2201/0338

Abstract: A package substrate structure includes a substrate, a metal base layer, a build-up film, a bonding layer, and a wiring unit. The metal base layer is disposed on the substrate. The build-up film is disposed on the metal base layer and is formed with trenches to expose the metal base layer. The build-up film includes an insulating material. The bonding layer is disposed on the build-up film and includes a graphene-metal composite. The graphene-metal composite includes a metal matrix, and a plurality of graphene nanostructures dispersed in the metal matrix and arranged among lattices of the metal matrix. The graphene nanostructures form covalent bonds with each other. The wiring unit is bonded to the build-up film through the bonding layer and fills the trenches so as to be electrically connected to the metal base layer. The wiring unit is formed with a wiring pattern on the build-up film.

公开(公告)号：US11751329B2

公开(公告)日：2023-09-05

申请号：US17960830

申请日：2022-10-06

Applicant: AUO Corporation

Inventor： Tsung-Ying Ke ,  Chun-Nan Chen ,  Zih-Shuo Huang

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K1/0283 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/09 ,  H05K1/095 ,  H05K1/111 ,  H05K2201/0314 ,  H05K2201/0338 ,  H05K2201/09263 ,  H05K2201/10106

Abstract: A stretchable electronic device includes a substrate, a plurality of electronic elements, and a conductive wiring. The electronic elements and the conductive wiring are disposed on the substrate, and the conductive wiring is electrically connected to the electronic elements. The conductive wiring is formed by stacking an elastic conductive layer and a non-elastic conductive layer. A fracture strain of the elastic conductive layer is greater than a fracture strain of the non-elastic conductive layer, and the non-elastic conductive layer includes a plurality of first fragments which are separated from one another.

公开(公告)号：US11723153B2

公开(公告)日：2023-08-08

申请号：US17653054

申请日：2022-03-01

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Mi Bae ,  Soon Gyu Kwon ,  Sang Hwa Kim ,  Sang Young Lee ,  Jin Hak Lee ,  Han Su Lee ,  Dong Hun Jeong ,  In Ho Jeong ,  Dae Young Choi ,  Jung Ho Hwang

IPC: H05K1/11 ,  H05K3/24 ,  H05K3/18 ,  H05K3/10 ,  H05K1/02 ,  C25D3/48 ,  C25D5/02 ,  C25D5/48 ,  C25D7/12 ,  H05K1/09 ,  C25D3/38

CPC classification number: H05K3/244 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/0296 ,  H05K1/09 ,  H05K1/11 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  C25D3/38 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/099 ,  H05K2201/0989 ,  H05K2203/1184

Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

公开(公告)号：US20230247763A1

公开(公告)日：2023-08-03

申请号：US18297857

申请日：2023-04-10

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Koji NITTA ,  Yasushi MOCHIDA ,  Yoshio OKA ,  Shoichiro SAKAI ,  Tadahiro KAIBUKI ,  Junichi OKAUE

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/36 ,  H05K3/24

CPC classification number: H05K1/118 ,  H05K1/0265 ,  H05K1/0298 ,  H05K3/241 ,  H05K3/361 ,  H05K2201/094 ,  H05K2201/0338 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2203/0723

Abstract: A flexible printed circuit board includes a base film having an insulating property and a plurality of interconnects laminated to at least one surface side of the base film. The plurality of interconnects includes a first interconnect and a second interconnect in a same plane. An average thickness of the second interconnect being greater than an average thickness of the first interconnect. A ratio of the average thickness of the second interconnect to the average thickness of the first interconnect is greater than or equal to 1.5 and less than or equal to 50. The first interconnect includes a first conductive underlayer and a first plating layer, and the second interconnect includes a second conductive underlayer, a second plating layer, and a third plating layer.

公开(公告)号：US11706870B2

公开(公告)日：2023-07-18

申请号：US17503690

申请日：2021-10-18

Applicant: Cisco Technology, Inc.

Inventor： Joel Goergen ,  Jessica Kiefer ,  Alpesh Umakant Bhobe ,  Kameron Rose Hurst ,  D. Brice Achkir ,  Amendra Koul ,  Scott Hinaga ,  David Nozadze

IPC: H05K3/46 ,  H05K1/09

CPC classification number: H05K1/09 ,  H05K3/4644 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2203/1545

Abstract: A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.

公开(公告)号：US20190223286A1

公开(公告)日：2019-07-18

申请号：US16324504

申请日：2017-08-10

Applicant: Schweizer Electronic AG ,  Continental Automotive GmbH

Inventor： Hubert Trageser ,  Alexander Neumann

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/06 ,  H05K3/24 ,  H05K3/34 ,  H05K3/38 ,  H05K3/42

CPC classification number: H05K1/0256 ,  H05K1/09 ,  H05K3/06 ,  H05K3/061 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/388 ,  H05K3/421 ,  H05K3/428 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/0769 ,  H05K2201/0989

Abstract: A circuit board (10, 10′, 10″) includes at last one insulating substrate layer (SL1, SL2, SL3, SL4, SL5) and a plurality of electrically conductive copper coats (C1, C2, C3) arranged on the at least one insulating substrate layer (SL1, SL2, SL3, SL4, SL5), wherein at least one of the electrically conductive copper coats (C1, C2, C3) is coated at least on both sides with a layer (HSI, HS2, HS3) made of a material for inhibiting electromigration, wherein on a layer (HS1, HS2) made of a material for inhibiting electromigration a further metal layer (M1, M2, M3, M3′) is provided, which is in turn coated with a further layer (HS3, HS3′) made of a material for inhibiting electromigration.

公开(公告)号：US20190124763A1

公开(公告)日：2019-04-25

申请号：US16229948

申请日：2018-12-21

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Shigeru MICHIWAKI

IPC: H05K1/02 ,  H05K3/14 ,  H05K3/00 ,  H05K3/42 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K1/0284 ,  H05K1/0326 ,  H05K1/09 ,  H05K3/0014 ,  H05K3/0023 ,  H05K3/14 ,  H05K3/181 ,  H05K3/389 ,  H05K3/426 ,  H05K2201/0129 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/072 ,  H05K2203/124 ,  H05K2203/1461

Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.

公开(公告)号：US20190043662A1

公开(公告)日：2019-02-07

申请号：US16156184

申请日：2018-10-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Issei Yamamoto

IPC: H01F27/36 ,  H03H7/01 ,  H01G4/40 ,  H01G4/005 ,  H01G4/12 ,  H01F27/40

CPC classification number: H01F27/36 ,  H01F17/0013 ,  H01F27/40 ,  H01F2017/0026 ,  H01F2017/008 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/40 ,  H03H7/0115 ,  H03H2001/0085 ,  H05K1/0218 ,  H05K1/092 ,  H05K3/248 ,  H05K3/4629 ,  H05K2201/0338 ,  H05K2201/0715

Abstract: The present disclosure is intended to reduce connection resistance between a shield film and a ground electrode, and to improve characteristics of the shield film. A high frequency component 1a includes a ceramic substrate 2, a ground electrode 3a disposed inside the ceramic substrate 2, a shield film 4 covering an upper surface 2a and lateral surfaces 2c of the ceramic substrate 2, and connecting portions 6a connecting the ground electrode 3a and the shield film 4, wherein the ground electrode 3a is formed using a conductive paste that contains a metal ingredient, powder, and a material constituting the ceramic substrate 2, and a weight rate of a metal ingredient in the connecting portions 6a is higher than that of the metal ingredient in the ground electrode 3a.

公开(公告)号：US10057985B2

公开(公告)日：2018-08-21

申请号：US15617082

申请日：2017-06-08

Applicant: DENSO CORPORATION

Inventor： Kenji Ochi

IPC: H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K5/00

CPC classification number: H05K1/092 ,  H05K1/09 ,  H05K1/111 ,  H05K1/181 ,  H05K3/4007 ,  H05K5/0069 ,  H05K2201/0338 ,  H05K2201/10522 ,  H05K2201/10628 ,  H05K2201/10636

Abstract: A printed substrate includes a land that is to be soldered. The land includes a plating film that defines a surface of the land. The plating film includes a metal as a main constituent and a pi-acceptor molecule that is dispersed in the plating film. The pi-acceptor molecule has pi-acceptability and causes ligand field splitting equal to or greater than that of 2,2′-bipyridyl in spectrochemical series. A content of the pi-acceptor molecule in the plating film is equal to or greater than 0.1 weight percent, in terms of carbon atoms, with respect to the metal of the plating film.