公开(公告)号：US11824042B2

公开(公告)日：2023-11-21

申请号：US17105272

申请日：2020-11-25

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/822 ,  H01L25/00 ,  H01L23/498 ,  H01L23/60 ,  H01L23/522 ,  H01L27/06 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L21/8221 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/60 ,  H01L24/32 ,  H01L25/50 ,  H01L27/0688 ,  H01L23/50 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/08147 ,  H01L2224/09181 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US11515291B2

公开(公告)日：2022-11-29

申请号：US16397202

申请日：2019-04-29

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20250142942A1

公开(公告)日：2025-05-01

申请号：US18906050

申请日：2024-10-03

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H10D84/03 ,  H01L21/768 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L25/065 ,  H10D88/00

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US20240345399A1

公开(公告)日：2024-10-17

申请号：US18408074

申请日：2024-01-09

Applicant: Adeia Semiconductor Inc.

Inventor： Ilyas Mohammed ,  Rajesh Katkar ,  Belgacem Haba

IPC: G02B27/01 ,  G02B27/14

CPC classification number: G02B27/0172 ,  G02B6/0035 ,  G02B6/0076 ,  G02B27/144 ,  G02B2027/0178

Abstract: An optical apparatus is provided comprising: first and second optical waveguides disposed in a substrate such that light reflected by a beam splitting optical element of the first waveguide passes between beam splitting elements of the second waveguide.

公开(公告)号：US12074092B2

公开(公告)日：2024-08-27

申请号：US17172756

申请日：2021-02-10

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz

IPC: H01L23/48 ,  G06F13/40 ,  H01L23/528

CPC classification number: H01L23/481 ,  G06F13/4027 ,  H01L23/528

Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.

公开(公告)号：US20240152743A1

公开(公告)日：2024-05-09

申请号：US18469910

申请日：2023-09-19

Applicant: Adeia Semiconductor Inc.

Inventor： Steven L. Teig ,  Kenneth Duong

IPC: G06N3/065 ,  G06F11/14 ,  G06F11/20 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/31 ,  H01L25/065

CPC classification number: G06N3/065 ,  G06F11/1423 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2051 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/3128 ,  H01L25/0657 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/16235

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

公开(公告)号：US11894345B2

公开(公告)日：2024-02-06

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/08 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06586 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/3025

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US11688776B2

公开(公告)日：2023-06-27

申请号：US17217104

申请日：2021-03-30

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz ,  David Edward Fisch

IPC: H01L21/76 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L23/00 ,  H01L23/538 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/4175 ,  H01L21/02532 ,  H01L21/76275 ,  H01L21/76283 ,  H01L23/538 ,  H01L24/11 ,  H01L24/13 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/13016

Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

公开(公告)号：US20230090121A1

公开(公告)日：2023-03-23

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20240266325A1

公开(公告)日：2024-08-08

申请号：US18379925

申请日：2023-10-13

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L21/822 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L25/00 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/8221 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/60 ,  H01L24/32 ,  H01L25/50 ,  H01L27/0688 ,  H01L23/50 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/08147 ,  H01L2224/09181 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.