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    Stacked IC structure with orthogonal interconnect layers
    1.
    发明授权
    Stacked IC structure with orthogonal interconnect layers 有权

    公开(公告)号：US11881454B2

    公开(公告)日：2024-01-23

    申请号：US17201732

    申请日：2021-03-15

    Applicant: ADEIA SEMICONDUCTOR INC.

    Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. Delacruz

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L21/822 ,  H01L27/06 ,  H01L23/522 ,  H01L25/065

    CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L23/50 ,  H01L23/5225 ,  H01L24/26 ,  H01L25/0657 ,  H01L27/0688 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08147 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/15311

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    Hard IP blocks with physically bidirectional passageways
    4.
    发明授权
    Hard IP blocks with physically bidirectional passageways 有权

    公开(公告)号：US12074092B2

    公开(公告)日：2024-08-27

    申请号：US17172756

    申请日：2021-02-10

    Applicant: ADEIA SEMICONDUCTOR INC.

    Inventor： Javier A. Delacruz

    IPC: H01L23/48 ,  G06F13/40 ,  H01L23/528

    CPC classification number: H01L23/481 ,  G06F13/4027 ,  H01L23/528

    Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.

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