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    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT
    23.
    发明申请
    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT 有权

    公开(公告)号：US20250096082A1

    公开(公告)日：2025-03-20

    申请号：US18369443

    申请日：2023-09-18

    Applicant: Infineon Technologies AG

    Inventor： Mei Yih Goh ,  Chee Voon Tan ,  Sung Hoe Yeong ,  Michael Stadler

    IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

    Abstract: An electrical interconnect clip includes a die interface portion that is adapted for mating in between two vertically stacked semiconductor dies, and a carrier connection portion that is configured to electrically connect the two vertically stacked semiconductor dies with a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite from the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface that are spaced apart from the outer edge sides of the electrical interconnect clip and surround a die attach area of the upper mating surface.

    POWER MODULE AND METHOD OF FABRICATING THE SAME
    24.
    发明申请
    POWER MODULE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250096069A1

    公开(公告)日：2025-03-20

    申请号：US18816500

    申请日：2024-08-27

    Applicant: Infineon Technologies AG

    Inventor： Adrian Lis ,  Thomas Schmid ,  Ewald Günther

    IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H02M1/32

    Abstract: A power module includes a substrate, one or more semiconductor dies mounted to the substrate, a first external power connection electrically connected to a first power terminal of at least one of the one or more semiconductor dies, and an encapsulant at least partially encapsulating the first external power connection. A portion of the first external power connection and at least parts of an outer surface of the substrate are exposed from the encapsulant. A heatsink is mounted to the first external power connection.

    ENHANCED OFFSET COMPENSATION TECHNIQUE FOR THERMAL CONDUCTIVITY SENSING OF A GAS CONCENTRATION SENSOR
    25.
    发明申请
    ENHANCED OFFSET COMPENSATION TECHNIQUE FOR THERMAL CONDUCTIVITY SENSING OF A GAS CONCENTRATION SENSOR 有权

    公开(公告)号：US20250093288A1

    公开(公告)日：2025-03-20

    申请号：US18817806

    申请日：2024-08-28

    Applicant: Infineon Technologies AG

    Inventor： Silviu-Antonio PIELEANU ,  Dan Ioan Dumitru STOICA ,  Dan-Alexandru MOCANU

    IPC: G01N27/12

    Abstract: A gas concentration sensor configured to measure a gas concentration of a target gas includes a reference chamber configured to contain a reference gas; a measurement chamber configured to contain the target gas; and a measurement circuit, configurable in a calibration mode and an operational mode, including a resistive bridge circuit including a first resistive element arranged in the reference chamber and a second resistive element arranged in the measurement chamber. The resistive bridge circuit is configured to receive an input voltage and generate a measurement signal based on the input voltage. During the calibration mode, the input voltage has a first voltage value at which the resistive bridge circuit has a negligible sensitivity to thermal conductivity such that the measurement signal is representative of an offset. The measurement circuit is configured to, during the operational mode, subtract the offset from the measurement signal to generate a compensated measurement signal.

    Semiconductor device including first gate electrode and second gate electrode
    27.
    发明授权
    Semiconductor device including first gate electrode and second gate electrode 有权

    公开(公告)号：US12255251B2

    公开(公告)日：2025-03-18

    申请号：US18212906

    申请日：2023-06-22

    Applicant: Infineon Technologies AG

    Inventor： Roman Baburske

    IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10

    Abstract: A semiconductor device includes: a drift region of a first conductivity type in a semiconductor body having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; and trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into mesas. The trenches include: a first trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; a second trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; and a third trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes. Additional semiconductor device embodiments are described herein.

    Electronic device with multi-layer contact and system
    28.
    发明授权
    Electronic device with multi-layer contact and system 有权

    公开(公告)号：US12255168B2

    公开(公告)日：2025-03-18

    申请号：US18509357

    申请日：2023-11-15

    Applicant: Infineon Technologies AG

    Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

    IPC: H01L29/43 ,  H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L29/45

    Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

    VERTICAL POWER SEMICONDUCTOR DEVICE INCLUDING SILICON CARBIDE (SIC) SEMICONDUCTOR BODY
    29.
    发明申请
    VERTICAL POWER SEMICONDUCTOR DEVICE INCLUDING SILICON CARBIDE (SIC) SEMICONDUCTOR BODY 有权

    公开(公告)号：US20250089323A1

    公开(公告)日：2025-03-13

    申请号：US18827272

    申请日：2024-09-06

    Applicant: Infineon Technologies AG

    Inventor： Thomas AICHINGER ,  Dethard PETERS ,  Michael HELL ,  Andreas HÜRNER

    IPC: H01L29/16 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78

    Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

    Error Correction Device and Method for Correcting a Data Block
    30.
    发明申请
    Error Correction Device and Method for Correcting a Data Block 有权

    公开(公告)号：US20250088205A1

    公开(公告)日：2025-03-13

    申请号：US18882947

    申请日：2024-09-12

    Applicant: Infineon Technologies AG

    Inventor： Berndt Gammel ,  Rainer Göttfert ,  Stefan Seidl ,  Martin Schläffer

    IPC: H03M13/29 ,  H03M13/15

    Abstract: A method for correcting a data block comprises correcting the data block in one or more iterations, each iteration comprising applying a first error correction and error detection method in accordance with a first code to a first set of vectors, wherein vectors of the first set of vectors for which t errors are detected but cannot be corrected by the error correction in accordance with the first code are marked, and applying a second error correction and error detection method in accordance with a second code to at least one portion of a second set of vectors, wherein the correction of vectors of the second set of vectors which contain one or more errors that could be corrected in accordance with the second code but relate to entries that do not belong to vectors of the marked vectors of the first set of vectors are skipped.

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