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    3D DOME WAFER-LEVEL PACKAGE FOR OPTICAL MEMS MIRROR WITH REDUCED FOOTPRINT
    2.
    发明公开
    3D DOME WAFER-LEVEL PACKAGE FOR OPTICAL MEMS MIRROR WITH REDUCED FOOTPRINT 审中-公开

    公开(公告)号：US20230288695A1

    公开(公告)日：2023-09-14

    申请号：US17690158

    申请日：2022-03-09

    Applicant: Infineon Technologies AG

    Inventor： Andre BROCKMEIER ,  Ulf BARTL ,  Kurt SORSCHAG

    IPC: G02B26/08 ,  B81B7/00 ,  B81C1/00

    CPC classification number: G02B26/085 ,  B81B7/0038 ,  B81B7/0067 ,  B81C1/00285 ,  B81C1/00317 ,  B81B2201/042 ,  B81C2203/0118

    Abstract: A microelectromechanical systems (MEMS) mirror package assembly includes: a MEMS wafer including a stator portion and a rotor portion that includes a MEMS mirror configured to rotate about an axis, wherein the MEMS mirror is suspended over a back cavity, wherein the MEMS wafer defines a first portion of the back cavity; a spacer wafer, wherein the backside of the spacer wafer is bonded to the frontside of the MEMS wafer, wherein the spacer wafer defines a first portion of a front cavity arranged over the MEMS mirror; a transparent cover wafer, wherein the backside of the transparent cover wafer is bonded to the frontside of the spacer wafer, wherein the transparent cover wafer includes a transparent dome structure arranged over the MEMS mirror and defining a second portion of the front cavity. The center of the MEMS mirror is arranged substantially at a vertex of the transparent dome structure.

    METHOD WITH STEALTH DICING PROCESS FOR FABRICATING MEMS SEMICONDUCTOR CHIPS
    3.
    发明申请
    METHOD WITH STEALTH DICING PROCESS FOR FABRICATING MEMS SEMICONDUCTOR CHIPS 有权

    公开(公告)号：US20210309513A1

    公开(公告)日：2021-10-07

    申请号：US17188082

    申请日：2021-03-01

    Applicant: Infineon Technologies AG

    Inventor： Andre BROCKMEIER ,  Stephan HELBIG ,  Adolf KOLLER

    IPC: B81C1/00 ,  G02B26/08 ,  G02B26/10

    Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

    METHOD WITH MECHANICAL DICING PROCESS FOR PRODUCING MEMS COMPONENTS
    6.
    发明申请
    METHOD WITH MECHANICAL DICING PROCESS FOR PRODUCING MEMS COMPONENTS 有权

    公开(公告)号：US20210253421A1

    公开(公告)日：2021-08-19

    申请号：US17248799

    申请日：2021-02-08

    Applicant: Infineon Technologies AG

    Inventor： Andre BROCKMEIER ,  Markus BERGMEISTER ,  Bernhard GOLLER ,  Daniel PIEBER ,  Sokratis SGOURIDIS

    IPC: B81C1/00

    Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.

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