Abstract:
An asymmetric bump structure for wafer is provided. First, the wafer includes multi-chip units each of which has an active surface. The asymmetric bump structure includes a conductive surface on the active surface, a conductive structure contacted the portion of the conductive surface and located on the both conductive surface and the active surface, and a conductive material contacted the conductive structure. The conductive material and the conductive structure contacted part of the conductive surface have respective geometric centers which are not on an identical vertical axis.
Abstract:
A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.
Abstract:
A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 μm is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.
Abstract:
The invention related to a method and circuit that is used to compensate for S-parameters of a passive circuit which do not satisfy passivity. The method includes the following steps: (1) getting S-parameters which do not satisfy passivity, these S-parameters being composed of an S-parameter matrix S; (2) computing matrix [S×S′], wherein matrix S′ is a complex conjugate transposed matrix of the S-parameter matrix S; (3) computing the eigenvalues of the matrix [S×S′], and choosing an eigenvalue Ψ whose real part real(Ψ) is the biggest; (4) computing a compensating value ξ, the compensating value ξ being equal to real(Ψ)1/2×(1+ε), wherein the ε is a very small positive number; and (5) dividing each of the S-parameters by the compensating value ξ to get the compensated S-parameters.
Abstract:
A computer enclosure includes a chassis with a plurality of heat generating components installed therein and an airflow guide structure. The airflow guide structure includes a fan and a duct attached to the fan. A pair of airflow outlets aligned with the fan is defined in the duct. The duct includes a plurality of pivot panels pivotally attached at airflow outlets. The pivot panels are configured to guide airflow from the fan to different positions of heat generating components in the chassis.
Abstract:
An electronic apparatus includes an enclosure (30), a circuit board (40), a fan module (20), and an air guiding element (10) mounted in the enclosure. The circuit board includes at least one heat generating component (41) thereon. The fan module has a fan (22) and an output opening (213) corresponding to the fan. The air guiding element comprises a resisting panel (11) and a guiding panel (12) comprises a free end that extends toward the output opening of the fan module. The at least one heat generating component and the output opening are on the same side of the resisting panel. The guiding panel defines a free end (127) and a connecting end (125) connecting the resisting panel. A plane defined by the ends of the guiding panel is aligned at an angle larger than 90 degrees relative to the resisting panel.
Abstract:
A circuit board assembly includes a circuit board with two heat dissipating assemblies mounted thereon and an L-shaped back plate attached to an underside of the circuit board. Each of the heat dissipating assembly includes at least a pair of securing members at opposite corners thereof. The back plate includes a first portion and a second portion each defining at least a pair of circular protrusions corresponding to the securing members of the heat dissipating assemblies.
Abstract:
A computer enclosure includes a chassis with a plurality of heat generating components installed therein and an airflow guide structure. The airflow guide structure includes a fan and a duct attached to the fan. A pair of airflow outlets aligned with the fan is defined in the duct. The duct includes a plurality of pivot panels pivotally attached at airflow outlets. The pivot panels are configured to guide airflow from the fan to different positions of heat generating components in the chassis.
Abstract:
A mounting apparatus for mounting a heat sink on a board, includes a first locking hole defined in the heat sink, a second locking hole defined in the board, and a locking member. The locking member includes a base and a rod. The base defines a hole. A bottom of the base forms a pair of separated elastic claws around the hole. The elastic claws are inserted through the first and second locking holes. The rod includes an expanded portion. The rod slides in the hole of the base with the expanded portion located inbetween the claws to expand the claws outwards to be larger than the second locking hole to lock the locking member on the board and to mount the heat sink on the board.
Abstract:
A circuit board is provided for improving signal quality, including a signal plane for a plurality of signal traces arranged thereon and a ground plane formed by a plurality of tiles connected to each other in an array. Each tile is formed by ground traces. Different line segments of a signal trace mapped on the ground plane cross ground traces of the tiles at similar angles, thereby minimizing interaction between the ground traces and the signal traces to reduce differences in impedances of the signal traces.