公开(公告)号：US11467773B2

公开(公告)日：2022-10-11

申请号：US17177214

申请日：2021-02-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Cheng Li ,  Yu-Chung Shen ,  Nien-Hung Lin

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F11/10

Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.

公开(公告)号：US11467758B2

公开(公告)日：2022-10-11

申请号：US16425942

申请日：2019-05-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chieh Yang ,  Yi-Hsuan Lin ,  Tai-Yuan Huang ,  Ping-Chuan Lin

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.

公开(公告)号：US11430538B1

公开(公告)日：2022-08-30

申请号：US17195547

申请日：2021-03-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Pochiao Chou ,  Cheng-Che Yang

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.

公开(公告)号：US20220269581A1

公开(公告)日：2022-08-25

申请号：US17200910

申请日：2021-03-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien Chang Tseng

IPC: G06F11/36 ,  G06F11/30 ,  G06F11/32

Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.

公开(公告)号：US11409596B1

公开(公告)日：2022-08-09

申请号：US17184611

申请日：2021-02-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.

公开(公告)号：US11372590B2

公开(公告)日：2022-06-28

申请号：US17105521

申请日：2020-11-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chia-Hsiung Lai

IPC: G06F3/06

Abstract: A memory control method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit in response to a first read command from a host system; performing a first decoding operation on the first data to obtain decoded data corresponding to the first data; storing the decoded data corresponding to the first data in a buffer memory; reading second data from the first physical unit in response to a second read command from the host system; performing a second decoding operation on the second data; and in response to failure of the second decoding operation, searching the buffer memory for the decoded data corresponding to the first data to replace the reading of the second data.

公开(公告)号：US11216334B1

公开(公告)日：2022-01-04

申请号：US17002783

申请日：2020-08-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Jeng Wang ,  Shao-Hung Lu

IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G06F3/06

Abstract: A data reading method is provided. The method includes: according to a first read command received from a host system, sending a first read command sequence, which is configured to instruct a reading of a plurality of physical units of the rewritable non-volatile memory module to obtain first data; identifying data stored in at least one first physical unit in the physical units as uncorrectable data according to the first data; according to a second command received from the host system, sending a second read command sequence, which is configured to instruct a reading of the physical units of the rewritable non-volatile memory module to obtain second data; generating response data corresponding to the second read command according to the second data and padding data, which is configured to replace the data read from the at least one first physical unit; and transmitting the response data to the host system.

公开(公告)号：US20210397347A1

公开(公告)日：2021-12-23

申请号：US16921874

申请日：2020-07-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Hsiao-Yi Lin ,  Yu-Siang Yang

IPC: G06F3/06

Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

公开(公告)号：US20210257033A1

公开(公告)日：2021-08-19

申请号：US16805848

申请日：2020-03-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Bo-Jing Lin ,  Yu-Chiang Liao

IPC: G11C16/32 ,  H03L7/081 ,  H03L7/093 ,  H04L7/00

Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.

公开(公告)号：US11086564B2

公开(公告)日：2021-08-10

申请号：US15788809

申请日：2017-10-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Hsien Liu

IPC: G06F3/06 ,  G06F11/30 ,  G06F1/20 ,  G06F12/02

Abstract: A temperature control method is provided according to an exemplary embodiment of the invention. The method includes: sensing a temperature by a temperature sensor and obtaining a temperature value; performing a cooling-down operation based on a first cooling-down level and updating a level parameter to a first level parameter if the temperature value reaches a first threshold value; and performing the cooling-down operation based on a second cooling-down level according to the first level parameter and updating the level parameter to a second level parameter if the temperature value is not less than the first threshold value during a first time range after the cooling-down operation based on the first cooling-down level is performed, and a cooling-down ability of the cooling-down operation performed based on the second cooling-down level is higher than a cooling-down ability of the cooling-down operation performed based on the first cooling-down level.