公开(公告)号：US08186054B2

公开(公告)日：2012-05-29

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H01K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US20110048777A1

公开(公告)日：2011-03-03

申请号：US12547456

申请日：2009-08-25

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K1/16

CPC classification number: H05K1/188 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K3/025 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A component-embedded printed circuit board includes: a carrier plate having a metalized layer disposed thereon, an electronic component disposed on the metalized layer of the carrier plate, and a metal layer laminated onto the metalized layer having the electronic component disposed thereon by a dielectric film. The carrier plate is then removed to expose the metalized layer. At least one of the metal layer and the metalized layer is patterned to be a circuit layer.

Abstract translation: 嵌入部件的印刷电路板包括：载置板，其上设置有金属化层，设置在载体板的金属化层上的电子部件和层叠在金属化层上的金属层，该金属层具有通过电介质设置在其上的电子部件 电影。 然后移除载体板以露出金属化层。 将金属层和金属化层中的至少一个图案化为电路层。

公开(公告)号：US07488675B2

公开(公告)日：2009-02-10

申请号：US11684583

申请日：2007-03-09

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: H01L21/44

CPC classification number: H05K1/116 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09736 ,  Y10T29/41 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an IC board without a ring structure is provided. In the method, after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first deposited metal layer, and a portion of the second deposited metal layer (this portion of the second deposited metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second deposited metal layer, the first deposited metal layer, the metal layer, and the substrate at the innermost layer which are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, and to couple a conductive line to the core board through hole.

Abstract translation: 提供一种制造没有环形结构的IC板的方法。 在该方法中，在芯板（包括芯通孔）完成之后，第二图案光致抗蚀剂层用于掩蔽第一沉积金属层，并且第二沉积金属层的一部分（第二次 沉积的金属层电连接到芯通孔的导电电路）。 然后，去除未被第二图案光刻胶层掩蔽的第二沉积金属层，第一沉积金属层，金属层和最内层的基板。 结果，基板被暴露以形成无环结构，并且将导电线耦合到芯板通孔。

公开(公告)号：US20080314622A1

公开(公告)日：2008-12-25

申请号：US11766194

申请日：2007-06-21

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K1/03 ,  H05K3/00

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US20080303150A1

公开(公告)日：2008-12-11

申请号：US11760079

申请日：2007-06-08

Applicant: Chien-Wei Chang ,  Ting-Hao Lin

Inventor： Chien-Wei Chang ,  Ting-Hao Lin

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L21/4846 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A high-density fine line circuit structure mainly includes: a first semiconductor device, an insulated layer on the same surface, an outer circuit layer above the first semiconductor device, and a solder mask formed on the outer circuit layer. The surface which is not covered by the solder mask can be made to be a pad, and electrically connected with a second semiconductor device. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.

Abstract translation: 高密度细线电路结构主要包括：第一半导体器件，同一表面上的绝缘层，第一半导体器件上方的外电路层和形成在外电路层上的焊接掩模。 未被焊接掩模覆盖的表面可以制成焊盘，并与第二半导体器件电连接。 暴露的细线电路层是填充锡球的锡球垫。 使用电镀而不是蚀刻方法来形成细线电路层，并且去除在制造过程期间或结束时需要的载体和金属阻挡层，以增加用于实现该目的的物体的布线密度 高密度。

公开(公告)号：US20080216313A1

公开(公告)日：2008-09-11

申请号：US11684583

申请日：2007-03-09

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: H05K3/10

CPC classification number: H05K1/116 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09736 ,  Y10T29/41 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an IC board without a ring structure is provided, in which after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first depositing metal layer, and portion of the second depositing metal layer (this portion of the second depositing metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second depositing metal layer, the first depositing metal layer, the metal layer, and even to the substrate at the innermost layer which are for the portion that are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, but which is to couple a conductive line to the core board through hole.

Abstract translation: 提供一种用于制造没有环形结构的IC板的方法，其中在芯板（包括芯通孔）完成之后，使用第二图案光致抗蚀剂层来掩蔽第一沉积金属层，并将部分 第二沉积金属层（第二沉积金属层的该部分电耦合到芯通孔的导电电路）。 之后，去除第二沉积金属层，第一沉积金属层，金属层，甚至去除未被第二图案光刻胶层掩蔽的部分的最内层的基板。 结果，基板被暴露以形成无环结构，但是将导电线耦合到芯板通孔。

公开(公告)号：US08471375B2

公开(公告)日：2013-06-25

申请号：US11772208

申请日：2007-06-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin

Inventor： Chien-Wei Chang ,  Ting-Hao Lin

IPC: H01L23/02

CPC classification number: H01L21/4846 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/205 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.

Abstract translation: 高密度细线结构主要包括：具有相似结构的两个板和用于梳理两个板的电介质膜。 两块板之间的半导体器件相互相对，两块板组合起来。 两个板各自包括细线电路，同一表面上的绝缘层，以及安装在细线电路上方的半导体器件。 未被焊接掩模覆盖的电路的表面被制成焊盘。 衬垫填充有用于与另一半导体器件电连接的锡球。 使用电镀而不是蚀刻方法来形成细线电路层，并且去除在制造过程期间或结束时需要的载体和金属阻挡层，以增加用于实现该目的的物体的布线密度 高密度。

公开(公告)号：US20120231621A1

公开(公告)日：2012-09-13

申请号：US13043463

申请日：2011-03-09

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC: H01L21/28

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

Abstract translation: 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或两次图案化步骤中，在电介质层的开口中形成焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊垫的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US07871892B2

公开(公告)日：2011-01-18

申请号：US12479811

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: H01L21/20

CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

公开(公告)号：US07807034B2

公开(公告)日：2010-10-05

申请号：US11734274

申请日：2007-04-12

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: C25D5/02

CPC classification number: H05K3/423 ,  H05K3/0035 ,  H05K3/025 ,  H05K3/205 ,  H05K3/242 ,  H05K3/382 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1152

Abstract: A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.

Abstract translation: 本文公开了一种未蚀刻电路板的制造方法，其采用具有金属阻挡层和电镀铜层的金属基板来传输电流以形成电路层。 在电镀铜层上形成图案化的光致抗蚀剂层以限定电路层的位置，并通过电镀在电路板上形成电路或导电通孔。 在电路层上进一步形成电镀镍层或电镀金层，以保护电路并提高细线能力。 在处理过程中或之后，去除金属基板，金属阻挡层和电镀铜层以扩大布线空间，从而可以获得高密度电路板。