公开(公告)号：US09691480B2

公开(公告)日：2017-06-27

申请号：US15205882

申请日：2016-07-08

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US09570459B2

公开(公告)日：2017-02-14

申请号：US14314622

申请日：2014-06-25

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  G11C16/34

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

Abstract translation: 在一个示例中，设备包括垂直堆叠的存储器单元。 垂直堆栈的每个存储单元可以包括多于一个存储元件。 第一垂直栅极线可以耦合到每个存储器单元中的存储器元件中的第一个，并且第二垂直栅极线可以耦合到每个存储器单元中的第二个存储器元件。 第一垂直栅极线可以与第二垂直栅极线电隔离。

公开(公告)号：US20160379692A1

公开(公告)日：2016-12-29

申请号：US15197482

申请日：2016-06-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US09401202B2

公开(公告)日：2016-07-26

申请号：US14568025

申请日：2014-12-11

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C11/419 ,  G11C5/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract translation: 本发明的实施例大体上涉及半导体和存储器技术，更具体地涉及系统，集成电路和保持存储器元件的状态的方法，该数据与使用其他存储器元件的可变存取信号幅度的数据操作相关联，例如在第三 三维存储技术。 在一些实施例中，存储器件可以包括具有电阻存储元件的交叉点阵列。 访问信号发生器可以修改信号的幅度以产生用于信号访问与字线和位线的子集相关联的电阻性存储器元件的修改幅度。 跟踪信号发生器被配置为跟踪信号的经修改的幅度，并将跟踪信号施加到与其他子位位线相关联的其他电阻性存储元件，跟踪信号具有与信号的修改幅度不同的量级 。

公开(公告)号：US09312307B2

公开(公告)日：2016-04-12

申请号：US14568802

申请日：2014-12-12

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US09129668B2

公开(公告)日：2015-09-08

申请号：US14476632

申请日：2014-09-03

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C11/34 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  B82Y30/00 ,  G11C7/04

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。 在一些实施例中，存储器单元基于第三维存储器技术。 在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。 集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

公开(公告)号：US20140369151A1

公开(公告)日：2014-12-18

申请号：US14312022

申请日：2014-06-23

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C8/08 ,  G11C8/10

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

公开(公告)号：US20140367629A1

公开(公告)日：2014-12-18

申请号：US14476604

申请日：2014-09-03

Applicant: Unity Semiconductor Corporation

Inventor： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

IPC: H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract translation: 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。

公开(公告)号：US20140219006A1

公开(公告)日：2014-08-07

申请号：US14150521

申请日：2014-01-08

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器 直接位于包含数据访问电路的FEOL基板之上。 在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。 访问信号发生器可以被配置为修改信号的大小以产生用于信号的修改的幅度，以访问与字线和位线的子集相关联的电阻性存储器元件。 修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

公开(公告)号：US20140140122A1

公开(公告)日：2014-05-22

申请号：US14024946

申请日：2013-09-12

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau

IPC: G11C5/06 ,  G11C13/00

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract translation: 本发明的实施例大体上涉及半导体和存储器技术，更具体地涉及系统，集成电路和保持存储器元件的状态的方法，该数据与使用其他存储器元件的可变存取信号幅度的数据操作相关联，例如在第三 三维存储技术。 在一些实施例中，存储器件可以包括具有电阻存储元件的交叉点阵列。 访问信号发生器可以修改信号的幅度以产生用于信号访问与字线和位线的子集相关联的电阻性存储器元件的修改幅度。 跟踪信号发生器被配置为跟踪信号的经修改的幅度，并将跟踪信号施加到与其他子位位线相关联的其他电阻性存储元件，跟踪信号具有与信号的修改幅度不同的量级 。