公开(公告)号：US12166099B2

公开(公告)日：2024-12-10

申请号：US18217739

申请日：2023-07-03

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  C23C16/34 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US12094686B2

公开(公告)日：2024-09-17

申请号：US18188255

申请日：2023-03-22

Applicant: ASM IP HOLDING B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi P. Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: H01L21/311 ,  C23F1/12 ,  C23G5/00 ,  H01J37/32 ,  H01L21/3213

CPC classification number: H01J37/32009 ,  C23F1/12 ,  C23G5/00 ,  H01L21/31116 ,  H01L21/32135

Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

公开(公告)号：US20240153817A1

公开(公告)日：2024-05-09

申请号：US18416147

申请日：2024-01-18

Applicant: ASM IP Holding B.V.

Inventor： Bhushan Zope ,  Kiran Shrestha ,  Shankar Swaminathan ,  Chiyu Zhu ,  Henri Jussila ,  Qi Xie

IPC: H01L21/768 ,  C23C16/02 ,  C23C16/04 ,  C23C16/14 ,  C23C16/455 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76876 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28568 ,  H01L21/76877 ,  H01L23/53266

Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

公开(公告)号：US20240096711A1

公开(公告)日：2024-03-21

申请号：US18522867

申请日：2023-11-29

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Chiyu Zhu ,  Kiran Shrestha ,  Pauline Calka ,  Oreste Madia ,  Jan Willem Maes ,  Michael Eugene Givens

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/823842 ,  H01L27/092 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.

公开(公告)号：US11908736B2

公开(公告)日：2024-02-20

申请号：US17700635

申请日：2022-03-22

Applicant: ASM IP Holding B.V.

Inventor： Bhushan Zope ,  Kiran Shrestha ,  Shankar Swaminathan ,  Chiyu Zhu ,  Henri Jussila ,  Qi Xie

IPC: H01L21/768 ,  H01L21/285 ,  C23C16/14 ,  C23C16/02 ,  H01L23/532 ,  C23C16/04 ,  C23C16/455

CPC classification number: H01L21/76876 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28568 ,  H01L21/76877 ,  H01L23/53266

Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

公开(公告)号：US20230374671A1

公开(公告)日：2023-11-23

申请号：US18357856

申请日：2023-07-24

Applicant: ASM IP HOLDING B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  C23F1/12 ,  H01L21/3213 ,  C09K13/00 ,  H01L21/311 ,  C09K13/08 ,  C09K13/10 ,  H01J37/32 ,  H01L21/3065

CPC classification number: C23F4/02 ,  C23F1/12 ,  H01L21/32135 ,  C09K13/00 ,  H01L21/31122 ,  C09K13/08 ,  C09K13/10 ,  H01J37/32009 ,  H01J37/3244 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US20230360964A1

公开(公告)日：2023-11-09

申请号：US18215249

申请日：2023-06-28

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/76832

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

公开(公告)号：US11695054B2

公开(公告)日：2023-07-04

申请号：US17411306

申请日：2021-08-25

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

CPC classification number: H01L29/517 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/0228 ,  H01L21/02175 ,  H01L21/02205 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/66568

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US11640899B2

公开(公告)日：2023-05-02

申请号：US17452156

申请日：2021-10-25

Applicant: ASM IP HOLDING B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi P. Haukka ,  Marko J. Tuominen ,  Chiyu Zhu

IPC: H01J37/32 ,  C23F1/12 ,  H01L21/311 ,  C23G5/00 ,  H01L21/3213

Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

公开(公告)号：US11447854B2

公开(公告)日：2022-09-20

申请号：US17078119

申请日：2020-10-23

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu

IPC: C23C14/54 ,  C23C14/00 ,  C23C14/34

Abstract: A process for the uniform controlled growth of materials on a substrate that directs a plurality of pulsed flows of a precursor into a reaction space of a reactor to deposit the thin film on the substrate. Each pulsed flow is a combination of a first pulsed subflow and a second pulsed subflow of the same precursor, wherein a pulse profile of the second pulsed subflow overlaps at least a portion of a latter half of a pulse profile of the first pulsed subflow having a non-uniform pulse profile.