公开(公告)号：US09711397B1

公开(公告)日：2017-07-18

申请号：US15140955

申请日：2016-04-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Nikolaos Bekiaris ,  Mehul Naik ,  Zhiyuan Wu

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/53209

Abstract: Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

公开(公告)号：US20250132165A1

公开(公告)日：2025-04-24

申请号：US18382326

申请日：2023-10-20

Applicant: Applied Materials, Inc.

Inventor： Jiajie Cen ,  Feng Q. Liu ,  Zheng Ju ,  Zhiyuan Wu ,  Kevin Kashefi ,  Mark Saly ,  Xianmin Tang

IPC: H01L21/311

Abstract: Methods of removing molybdenum oxide from a surface of a substrate comprise exposing the substrate having a molybdenum oxide layer on the substrate to a halide etchant having the formula RmSiX4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL) process, and the substrate contains a low-k dielectric material.

公开(公告)号：US20250112090A1

公开(公告)日：2025-04-03

申请号：US18979075

申请日：2024-12-12

Applicant: Applied Materials, Inc.

Inventor： Ge Qu ,  Zhiyuan Wu ,  Feng Chen ,  Carmen Leal Cervantes ,  Yong Jin Kim ,  Kevin Kashefi ,  Xianmin Tang ,  Wenjing Xu ,  Lu Chen ,  Tae Hong Ha

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US20240420966A1

公开(公告)日：2024-12-19

申请号：US18211044

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Wu ,  Zheng Ju ,  Feng Chen ,  Kevin Kashefi ,  Feng Q. Liu ,  Jeffrey W. Anthis

IPC: H01L21/3213 ,  H01L21/3205

Abstract: Embodiments of the disclosure relate to methods of etching a copper material. In some embodiments, the copper material is exposed to a halide reactant to form a copper halide species. The substrate is then heated to remove the copper halide species. In some embodiments, the etching methods are performed at relatively low temperatures. Additional embodiments of the disclosure relate to methods of copper gapfill. In some embodiments, a copper material within a substrate feature is exposed to a halide reactant to form a copper halide species. The copper halide species is then heated and flowed to fill at least a portion of the substrate feature. The reflow methods are performed at lower temperatures than similar reflow methods without formation of the copper halide species.

公开(公告)号：US11990368B2

公开(公告)日：2024-05-21

申请号：US17848162

申请日：2022-06-23

Applicant: Applied Materials, Inc.

Inventor： Mehul B. Naik ,  Zhiyuan Wu

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089

Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

公开(公告)号：US20230072614A1

公开(公告)日：2023-03-09

申请号：US17466732

申请日：2021-09-03

Applicant: Applied Materials, Inc.

Inventor： Ge Qu ,  Zhiyuan Wu ,  Feng Chen ,  Carmen Leal Cervantes ,  Yong Jin Kim ,  Kevin Kashefi ,  Xianmin Tang

IPC: H01L21/768

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US11171046B2

公开(公告)日：2021-11-09

申请号：US16837365

申请日：2020-04-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Feng Chen ,  Yufei Hu ,  Wenjing Xu ,  Gang Shen ,  Zhiyuan Wu ,  Tae Hong Ha

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Methods and apparatus for forming an interconnect structure, the method including selectively depositing two or more capping layers atop a top surface of a via within a low-k dielectric layer, wherein the two or more capping layers include a first layer of ruthenium and a second layer of cobalt.

公开(公告)号：US11043415B2

公开(公告)日：2021-06-22

申请号：US16564489

申请日：2019-09-09

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Wu ,  Nikolaos Bekiaris ,  Mehul B. Naik ,  Jin Hee Park ,  Mark Hyun Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/288 ,  H01L21/285 ,  H01L21/67

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

公开(公告)号：US10727119B2

公开(公告)日：2020-07-28

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Feiyue Ma ,  Yu Lei ,  Kai Wu ,  Mehul B. Naik ,  Zhiyuan Wu ,  Vikash Banthia ,  Hua Ai

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

公开(公告)号：US20180144973A1

公开(公告)日：2018-05-24

申请号：US15800784

申请日：2017-11-01

Applicant: Applied Materials, Inc.

Inventor： Weifeng Ye ,  Jiang Lu ,  Feng Chen ,  Zhiyuan Wu ,  Kai Wu ,  Vikash Banthia ,  He Ren ,  Sang Ho Yu ,  Mei Chang ,  Feiyue Ma ,  Yu Lei ,  Keyvan Kashefizadeh ,  Kevin Moraes ,  Paul F. Ma ,  Hua Ai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7685 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 Å to about 60 Å.