公开(公告)号：US20140138803A1

公开(公告)日：2014-05-22

申请号：US13678577

申请日：2012-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L23/34 ,  H01L23/552 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。

公开(公告)号：US20140118959A1

公开(公告)日：2014-05-01

申请号：US14148873

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/04 ,  H05K13/00

CPC classification number: H01L23/04 ,  H01L25/11 ,  H01L2924/0002 ,  H05B41/28 ,  H05K13/00 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A chip-housing module is provided, the chip-housing module including a carrier configured to carry one or more chips; the carrier including a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; the carrier including a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance.

Abstract translation: 提供了一种芯片外壳模块，芯片外壳模块包括一个承载一个或多个芯片的载体; 所述载体包括第一多个开口，其中所述第一多个开口的每个开口被分隔第一预定距离，并且被配置为接收芯片连接，用于将位于第一电压值范围内的电压提供给 芯片; 所述载体包括第二多个开口，其中所述第二多个开口的每个开口分开第二预定距离，并且被配置为接收芯片连接，用于将位于第二电压值范围内的电压提供给 芯片; 并且其中由所述第一多个开口的一个开口和所述第二多个开口的一个开口组成的一对开口被分开与所述第一预定距离和所述第二预定距离中的至少一个不同的距离。

公开(公告)号：US20140097528A1

公开(公告)日：2014-04-10

申请号：US13645548

申请日：2012-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495 ,  H01L23/488 ,  H01L23/00

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。

公开(公告)号：US20140091401A1

公开(公告)日：2014-04-03

申请号：US14036019

申请日：2013-09-25

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/58

CPC classification number: H01L23/58 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/45012

Abstract: In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact; wherein the second gate pad is electrically connected to the second gate contact. The integrated circuit may further include a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; and a second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit.

Abstract translation: 在各种实施例中，提供了具有集成电路的功率半导体外壳。 集成电路可以包括：第一栅极焊盘和第二栅极焊盘; 以及第一栅极接触和第二栅极接触; 其中所述第一栅极焊盘电连接到所述第一栅极触点; 其中所述第二栅极焊盘电连接到所述第二栅极触点。 集成电路还可以包括漏极接触表面，其中漏极接触表面连接到漏极接触; 以及与集成电路的漏极 - 接触表面电连接的第二漏极接触。

公开(公告)号：US12068213B2

公开(公告)日：2024-08-20

申请号：US17531867

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Thai Kee Gan ,  Sanjay Kumar Murugan ,  Ralf Otremba

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/565 ,  H01L23/296 ,  H01L23/3121 ,  H01L23/373 ,  H01L23/4951 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L2224/3702

Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

公开(公告)号：US11978693B2

公开(公告)日：2024-05-07

申请号：US17388248

申请日：2021-07-29

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Ulrich Froehler ,  Ralf Otremba ,  Andreas Riegler

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H05K1/18

CPC classification number: H01L23/49565 ,  H01L21/56 ,  H01L21/60 ,  H01L23/3107 ,  H05K1/182

Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

公开(公告)号：US20230402423A1

公开(公告)日：2023-12-14

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11715719B2

公开(公告)日：2023-08-01

申请号：US16875531

申请日：2020-05-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11450642B2

公开(公告)日：2022-09-20

申请号：US17132585

申请日：2020-12-23

Applicant: Infineon Technologies AG

Inventor： Edmund Riedl ,  Wu Hu Li ,  Alexander Heinrich ,  Ralf Otremba ,  Werner Reiss

IPC: H01L23/00 ,  H01L23/498 ,  B23K1/00 ,  B23K1/20 ,  B23K35/26 ,  B23K35/28 ,  B23K101/38

Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

公开(公告)号：US20220148934A1

公开(公告)日：2022-05-12

申请号：US17501568

申请日：2021-10-14

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Ralf Otremba ,  Daniel Pedone ,  Bernd Schmoelzer

IPC: H01L23/16 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.