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公开(公告)号：US09465680B1
公开(公告)日：2016-10-11
申请号：US14721819
申请日：2015-05-26
Applicant: INTEL CORPORATION
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Angela D. Schmid , Kimberly C. Weier , Ahmad Yasin , Jason W. Brandt , Charlie J. Hewett , Seth Abraham , Matthew C. Merten
CPC classification number: G06F9/542 , G06F11/00 , G06F11/3024 , G06F11/3409
Abstract: A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.
Abstract translation: 描述了使用固定功能性能计数器实现性能监视的处理器和方法。 例如，设备的一个实施例包括：固定功能性能计数器，用于在处理设备中发生事件时递减或递增; 精确的基于事件的采样（PEBS）使能控制可通信地耦合到固定功能性能计数器; PEBS处理器，用于生成和存储PEBS记录，其包括在生成PEBS记录时定义处理设备的状态的架构元数据; 以及可通信地耦合到PEBS使能控制和PEBS处理器的非精确事件采样（NPEBS）模块，NPEBS模块使固定功能性能计数器达到指定值时使PEBS处理程序生成事件的PEBS记录 。
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公开(公告)号：US20160259646A1
公开(公告)日：2016-09-08
申请号：US15155204
申请日：2016-05-16
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael W. Chynoweth , Ofer Levy , Jason W. Brandt , Angela Schmid
CPC classification number: G06F9/3806 , G06F9/30058 , G06F9/30098 , G06F11/3419 , G06F11/348 , G06F2201/865 , G06F2201/88
Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.
Abstract translation: 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器。 所述处理设备还包括至少一个可通信地耦合到所述LBR计数器的寄存器，所述至少一个寄存器提供包括多个LBR入口的LBR结构。 多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储LBR的值的经过时间字段 反对创建LBR条目。
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23.发明公开公开(公告)号：US20240103914A1
公开(公告)日：2024-03-28
申请号：US17954411
申请日：2022-09-28
Applicant: Intel Corporation
Inventor： Russell J. Fenger , Rajshree A. Chabukswar , Benjamin Graniello , Monica Gupta , Guy M. Therien , Michael W. Chynoweth
IPC: G06F9/48 , G06F1/3228
CPC classification number: G06F9/4887 , G06F1/3228
Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.
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公开(公告)号：US10656697B2
公开(公告)日：2020-05-19
申请号：US15911577
申请日：2018-03-05
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
IPC: G06F1/32 , G06F11/34 , G06F11/30 , G06F1/3206
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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Patent Agency Ranking
公开(公告)号：US10592244B2
公开(公告)日：2020-03-17
申请号：US15423143
申请日：2017-02-02
Applicant: INTEL CORPORATION
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC: G06F9/30
Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
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公开(公告)号：US20190050041A1
公开(公告)日：2019-02-14
申请号：US15911577
申请日：2018-03-05
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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公开(公告)号：US20180253370A1
公开(公告)日：2018-09-06
申请号：US15972390
申请日：2018-05-07
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US20170371769A1
公开(公告)日：2017-12-28
申请号：US15194881
申请日：2016-06-28
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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公开(公告)号：US09690588B2
公开(公告)日：2017-06-27
申请号：US15155204
申请日：2016-05-16
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael W. Chynoweth , Ofer Levy , Jason W. Brandt , Angela Schmid
CPC classification number: G06F9/3806 , G06F9/30058 , G06F9/30098 , G06F11/3419 , G06F11/348 , G06F2201/865 , G06F2201/88
Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.
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