公开(公告)号：US09443807B2

公开(公告)日：2016-09-13

申请号：US14020117

申请日：2013-09-06

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Thomas Ostermann

IPC: H01L23/58 ,  H01L23/544 ,  H01L21/66 ,  H01L21/784 ,  H01L29/06

CPC classification number: H01L23/544 ,  H01L21/784 ,  H01L22/12 ,  H01L22/34 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/03

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract translation: 一种器件包括半导体芯片。 半导体芯片的前端的轮廓包括以大于90°的内角连接的两条线段和弧形线的折线。

公开(公告)号：US20160139077A1

公开(公告)日：2016-05-19

申请号：US14930295

申请日：2015-11-02

Applicant: Infineon Technologies AG

Inventor： Sabine Gruber ,  Thomas Aichinger ,  Stefan Krivec ,  Thomas Ostermann

IPC: G01N27/447 ,  G01N27/414 ,  G01N27/27 ,  G01N27/453

CPC classification number: G01N27/44704 ,  G01N27/27 ,  G01N27/414 ,  G01N27/453

Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.

Abstract translation: 用于分析电介质探针结构中的离子动力学的装置包括邻接电介质探针结构并被配置为向介电探针结构提供移动离子的离子储存器，电容器结构，被配置为沿着垂直方向在电介质探针结构中产生电场 以及电极结构，其被配置为沿着横向方向在介电探针结构中的移动离子上产生电泳力。 还提供了用于分析该装置的电介质探针结构中的离子动力学的方法。

公开(公告)号：US11695069B2

公开(公告)日：2023-07-04

申请号：US17316067

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4232

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US11018250B2

公开(公告)日：2021-05-25

申请号：US16404005

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US20200135564A1

公开(公告)日：2020-04-30

申请号：US16176403

申请日：2018-10-31

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Christian Westermeier ,  Jochen Hilsenbeck ,  Jens Peter Konrath ,  Boris Mayerhofer ,  Anatoly Sotnikov

IPC: H01L21/78 ,  H01L21/04 ,  H01L29/16

Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

公开(公告)号：US20180197982A1

公开(公告)日：2018-07-12

申请号：US15915890

申请日：2018-03-08

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Radu Eugen Cazimirovici ,  Dietmar Kotz ,  Thomas Ostermann

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36 ,  H01L29/10 ,  H01L21/263 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7811 ,  H01L21/263 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.

公开(公告)号：US09941432B2

公开(公告)日：2018-04-10

申请号：US15167292

申请日：2016-05-27

Applicant: Infineon Technologies AG

Inventor： Stefan Clara ,  Thomas Grille ,  Ursula Hedenig ,  Peter Irsigler ,  Bernhard Jakoby ,  Ventsislav M. Lavchiev ,  Thomas Ostermann ,  Thomas Popp

IPC: H01L31/18 ,  H01L31/0352 ,  H01L33/06

CPC classification number: H01L31/035254 ,  H01L31/035209 ,  H01L31/035218 ,  H01L31/173 ,  H01L31/1812 ,  H01L31/1864 ,  H01L33/06 ,  H01L2933/0033

Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 μm and 10 μm or to absorb light with a light absorption maximum at a wavelength of between 2 μm and 10 μm.

公开(公告)号：US20140210052A1

公开(公告)日：2014-07-31

申请号：US14243332

申请日：2014-04-02

Applicant: Infineon Technologies AG

Inventor： Gerhard Prechtl ,  Andreas Peter Meiser ,  Thomas Ostermann

IPC: H01L29/735 ,  H01L29/66 ,  H01L27/082

CPC classification number: H01L29/735 ,  H01L27/082 ,  H01L29/1008 ,  H01L29/6625

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

Abstract translation: 根据实施例，提供一种用于制造半导体器件的方法。 该方法包括提供掩膜层，其在形成掺杂区域时用作注入掩模，并且当形成开口时形成开口和接触元件时用作蚀刻掩模。 接触元件与掺杂区域接触。