公开(公告)号：US09455343B2

公开(公告)日：2016-09-27

申请号：US14040574

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/66 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

Abstract translation: 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

公开(公告)号：US20160190282A1

公开(公告)日：2016-06-30

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/205 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/10

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09293560B2

公开(公告)日：2016-03-22

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Roza Kotlyar ,  Uday Shah ,  Charles C. Kuo

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US09231194B2

公开(公告)日：2016-01-05

申请号：US13996603

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  David L. Kencke ,  Robert S. Chau

IPC: H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less stable memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract translation: 实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的磁性隧道结（MTJ）; 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域（RA）产物，并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器，RA产物没有实质上高于具有仅具有单一氧化物层的MTJ的较不稳定的存储器。 本文描述了其它实施例。

公开(公告)号：US20150099349A1

公开(公告)日：2015-04-09

申请号：US14571579

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1−xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1−yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract translation: 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

公开(公告)号：US12058847B2

公开(公告)日：2024-08-06

申请号：US16888910

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC: H10B12/00 ,  H01L25/065

CPC classification number: H10B12/30 ,  H01L25/0657

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US11735595B2

公开(公告)日：2023-08-22

申请号：US17721236

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/42384 ,  H01L29/785

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

公开(公告)号：US20230022167A1

公开(公告)日：2023-01-26

申请号：US17382575

申请日：2021-07-22

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Van H. Le

IPC: H01L25/10 ,  H01L29/786 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

Abstract: Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

公开(公告)号：US11522011B2

公开(公告)日：2022-12-06

申请号：US16631156

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov ,  Brian S. Doyle ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20220246646A1

公开(公告)日：2022-08-04

申请号：US17721236

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.