公开(公告)号：US09942631B2

公开(公告)日：2018-04-10

申请号：US14866567

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Andrew J Herdrich ,  Patrick L. Connor ,  Dinesh Kumar ,  Alexander W Min ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B Shaw ,  Edwin Verplanke ,  Scott P. Dubal ,  James Robert Hearn

IPC: H04Q9/02 ,  H04L12/26 ,  H04L12/24

CPC classification number: H04Q9/02 ,  H04L41/5009 ,  H04L41/5019 ,  H04L43/08 ,  H04L43/10

Abstract: Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.

公开(公告)号：US20160378628A1

公开(公告)日：2016-12-29

申请号：US14752821

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Travis J. White ,  Scott P. Bobholz ,  Edwin Verplanke ,  Steven C. Franks ,  Vivek Garg ,  Ashok Raj ,  Guy G. Sotomayor ,  Jose A. Vargas ,  Pradeepsunder Ganesh ,  Stephen T. Palermo

IPC: G06F11/273 ,  G06F11/22

CPC classification number: G06F11/2236 ,  G06F11/008 ,  G06F11/27

Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.

Abstract translation: 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。

公开(公告)号：US12293231B2

公开(公告)日：2025-05-06

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin Sun ,  Yipeng Wang ,  Rahul R. Shah ,  Ren Wang ,  Sameh Gobriel ,  Hongjun Ni ,  Mrittika Ganguli ,  Edwin Verplanke

IPC: G06F9/50 ,  H04L47/11 ,  H04L47/12 ,  H04L47/125 ,  H04L12/70

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

公开(公告)号：US12292842B2

公开(公告)日：2025-05-06

申请号：US17486579

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/28 ,  H04L45/02 ,  H04L45/64 ,  H04L67/289 ,  H04L69/321

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

公开(公告)号：US12198186B2

公开(公告)日：2025-01-14

申请号：US17401575

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret Toll

IPC: G06Q40/03 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

公开(公告)号：US12067898B2

公开(公告)日：2024-08-20

申请号：US17256105

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Addicam V. Sanjay ,  Karthik Veeramani ,  Gabriel L Silva ,  Marcos P. Da Silva ,  Jose A. Avalos ,  Stephen T. Palermo ,  Glen J. Anderson ,  Meng Shi ,  Benjamin W. Bair ,  Pete A. Denman ,  Reese L. Bowes ,  Rebecca A. Chierichetti ,  Ankur Agrawal ,  Mrutunjayya Mrutunjayya ,  Gerald A. Rogers ,  Shih-Wei Roger Chien ,  Lenitra M. Durham ,  Giuseppe Raffa ,  Irene Liew ,  Edwin Verplanke

IPC: G06F9/38 ,  G06F9/455 ,  G06T19/00 ,  G09B5/06

CPC classification number: G09B5/067 ,  G06F9/3877 ,  G06F9/45558 ,  G06T19/006 ,  G06F2009/45562 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors: identify a student within the educational environment based on the sensor data: detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment: generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US20220182284A1

公开(公告)日：2022-06-09

申请号：US17505262

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Rashmin Patel ,  Monica Kenguva ,  Francesc Guim Bernat ,  Edwin Verplanke ,  Andrew J. Herdrich

IPC: H04L41/0816 ,  H04L41/14

Abstract: Technologies for analyzing and optimizing workloads (e.g., virtual network functions) executing on edge resources are disclosed. According to one embodiment disclosed herein, a compute device launches a virtualized system including a virtual network function and a performance manager, the performance manager to monitor a current resource usage of the virtual network function as a function of a performance profile. The compute device determines, in response to a determination that one or more quality-of-service (QoS) requirements is not satisfied, whether one or more resources from the platform are available for satisfying the QoS requirements. The compute device receives, in response to a determination that the one or more resources are available for satisfying the QoS requirements, the one or more resources and updates the performance profile as a function of the received resources.

公开(公告)号：US10771554B2

公开(公告)日：2020-09-08

申请号：US15721867

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi ,  Edwin Verplanke

IPC: G06F13/00 ,  H04L29/08 ,  G06F9/46 ,  G06F9/455

Abstract: Disclosed embodiments relate to cloud scaling with non-blocking, non-spinning cross-domain event synchronization and data communication. In an example, a processor includes a memory to store multiple virtual hardware thread (VHTR) descriptors, each including an architectural state, a monitored address range, a priority, and an execution state, fetch circuitry to fetch instructions associated with a plurality of the multiple VNFs, decode circuitry to decode the fetched instructions, scheduling circuitry to allocate and pin a VHTR to each of the plurality of VNFs, schedule execution of a VHTR on each of a plurality of cores, set the execution state of the scheduled VHTR; and in response to a monitor instruction received from a given VHTR, pause the given VHTR and switch in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range, trigger execution of the given VHTR.

公开(公告)号：US10713195B2

公开(公告)日：2020-07-14

申请号：US14997478

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Jr-Shian Tsai ,  Ravi L Sahita ,  Mesut A Ergin ,  Rajesh M Sankaran ,  Gilbert Neiger ,  Jun Nakajima ,  Edwin Verplanke ,  Barry E Huntley ,  Tsung-Yuan C Tai

IPC: G06F13/24 ,  G06F9/455

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.