公开(公告)号：US09804656B2

公开(公告)日：2017-10-31

申请号：US13631930

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Linda L. Hurd ,  Eric C. Samson

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3287 ,  Y02D10/16 ,  Y02D10/171

Abstract: Methods and apparatus relating to micro-architectural energy monitor event-assisted temperature sensing are described. In one embodiment, at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic are powered down or powered up based on a comparison of a temperature value, that is determined based on one or more micro-architectural events, and a threshold value. Other embodiments are also disclosed and claimed.

公开(公告)号：US09684541B2

公开(公告)日：2017-06-20

申请号：US14319099

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Arik Gihon ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Eric C. Samson ,  Michael Mishaeli ,  Yoni Aizik ,  Chen Ranel

IPC: G06T15/00 ,  G06F9/50 ,  G06F3/14

CPC classification number: G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

公开(公告)号：US09442558B2

公开(公告)日：2016-09-13

申请号：US14129950

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。

公开(公告)号：US09213395B2

公开(公告)日：2015-12-15

申请号：US14497736

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Aditya Navale

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3218 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Abstract translation: 一种方法包括检测触发条件，并且响应于检测到触发条件，降低施加到存储器控制器的图形控制器组件的电压。 电压的降低可能导致电压降低到维持图形控制器组件内的上下文信息所需的电压水平。

公开(公告)号：US11715174B2

公开(公告)日：2023-08-01

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F11/07 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/3887 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5083 ,  G06F9/5088 ,  G06F11/0793 ,  G06F2209/5017 ,  G06T2200/28 ,  G06T2210/52 ,  Y02D10/00

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US11467740B2

公开(公告)日：2022-10-11

申请号：US16715747

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F3/06 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US11270406B2

公开(公告)日：2022-03-08

申请号：US17099118

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

公开(公告)号：US11232536B2

公开(公告)日：2022-01-25

申请号：US16791514

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/60 ,  G06T1/20 ,  G06F8/41 ,  G06F12/0862

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US11048605B2

公开(公告)日：2021-06-29

申请号：US16526069

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34 ,  G06F1/324

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US10761585B2

公开(公告)日：2020-09-01

申请号：US16158190

申请日：2018-10-11

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3246 ,  G06F9/48

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.