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    Stacked dice systems
    27.
    发明授权
    Stacked dice systems 有权

    公开(公告)号：US10916524B2

    公开(公告)日：2021-02-09

    申请号：US16473570

    申请日：2017-11-29

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L27/06 ,  H01L27/08

    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.

    MICROELECTRONICS PACKAGE WITH A COMBINATION HEAT SPREADER/RADIO FREQUENCY SHIELD
    28.
    发明申请
    MICROELECTRONICS PACKAGE WITH A COMBINATION HEAT SPREADER/RADIO FREQUENCY SHIELD 审中-公开

    公开(公告)号：US20200027813A1

    公开(公告)日：2020-01-23

    申请号：US16453605

    申请日：2019-06-26

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/552

    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a base package, an ancillary package, and an electrically isolated metal layer. The base package may include a base die. The ancillary package may include an ancillary component. The ancillary package may be located on top of the base package. The electrically isolated metal layer may be located at least partially within a layer of the base package such that a portion of the electrically isolated metal layer contacts at least one surface of the base die and is located in between the base die and the ancillary component.

    Over-molded IC packages with embedded voltage reference plane and heater spreader
    29.
    发明授权
    Over-molded IC packages with embedded voltage reference plane and heater spreader 有权

    公开(公告)号：US10541200B2

    公开(公告)日：2020-01-21

    申请号：US15982912

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Mooi Ling Chang ,  Wen Wei Lum

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/367 ,  H01L23/50

    Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage. One or more conductive traces may connect the conductive features in the interior with conductive features in the periphery.

    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
    30.
    发明申请
    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH 审中-公开

    公开(公告)号：US20190355681A1

    公开(公告)日：2019-11-21

    申请号：US16473962

    申请日：2017-12-19

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

    IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48

    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

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