公开(公告)号：US20240136391A1

公开(公告)日：2024-04-25

申请号：US18047978

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Sanket S. Kelkar ,  Michael Mutch ,  Luca Fumagalli ,  Hisham Abdussamad Abbas ,  Brenda D. Kraus ,  Dojun Kim ,  Christopher W. Petz ,  Darwin Franseda Fan

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01G4/008 ,  H01G4/1218 ,  H01L27/10814 ,  H01L27/10852

Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.

公开(公告)号：US20240071832A1

公开(公告)日：2024-02-29

申请号：US17899166

申请日：2022-08-30

Applicant: Micron Technology, Inc

Inventor： Ronald Allen Weimer ,  Toshihiko Miyashita ,  Dan Mihai Mocuta ,  Christopher W. Petz

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/28518 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/7848

Abstract: A variety of applications can include apparatus having p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors with different metal silicide contacts. The active area of the NMOS transistor can include a first metal silicide having a first metal element, where the first metal silicide is a vertical lowest portion of a contact for the NMOS. The PMOS transistor can include a stressor source/drain region to a channel region of the PMOS transistor and a second metal silicide directly contacting the stressor source/drain region without containing the first metal element. The process flow to form the PMOS and NMOS transistors can enable making simultaneous contacts by a pre-silicide in the active area of the NMOS transistor, without affecting stressor source/drain regions in the PMOS transistor. The process flow and resulting structures for PMOS transistors and NMOS transistors can be used in various integrated circuits and devices.

公开(公告)号：US20220208767A1

公开(公告)日：2022-06-30

申请号：US17655257

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  Paul A. Paduano ,  Sanket S. Kelkar ,  Christopher W. Petz ,  Zhe Song ,  Vassil Antonov ,  Qian Tao

IPC: H01L27/108 ,  H01L21/285 ,  H01L49/02

Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

公开(公告)号：US20210327881A1

公开(公告)日：2021-10-21

申请号：US16851588

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Ke-Hung Chen ,  Christopher W. Petz ,  Pankaj Sharma ,  Yong Mo Yang

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/07

Abstract: Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210287990A1

公开(公告)日：2021-09-16

申请号：US16820046

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US10692572B2

公开(公告)日：2020-06-23

申请号：US16417320

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Christopher W. Petz ,  Everett Allen McTeer

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.

公开(公告)号：US20200013955A1

公开(公告)日：2020-01-09

申请号：US16552745

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Christopher W. Petz ,  Yongjun Jeff Hu ,  Scott E. Sills ,  D. V. Nirmal Ramaswamy

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L27/22 ,  C23C14/06 ,  C23C14/08 ,  C23C14/18 ,  C23C14/34 ,  C23C16/34 ,  C23C16/36 ,  C23C16/40 ,  C23C16/455

Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.

公开(公告)号：US10381072B2

公开(公告)日：2019-08-13

申请号：US14266456

申请日：2014-04-30

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Christopher W. Petz ,  Everett Allen McTeer

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.

公开(公告)号：US10354989B1

公开(公告)日：2019-07-16

申请号：US15980908

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

IPC: G11C11/34 ,  H01L27/02 ,  H01L23/532 ,  G11C5/06 ,  H01L27/12 ,  H01L21/82

Abstract: An integrated assembly having an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Also, an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Also, methods of forming integrated assemblies.

公开(公告)号：US09209388B2

公开(公告)日：2015-12-08

申请号：US14070423

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Christopher W. Petz ,  Dale W. Collins ,  Scott E. Sills ,  Shuichiro Yasuda

IPC: H01L45/00

CPC classification number: H01L45/1246 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608

Abstract: Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells.

Abstract translation: 一些实施例包括具有电极，电极上方的开关材料，开关材料上方的缓冲区域以及缓冲区域上方的离子储存器材料的存储器单元。 缓冲区域包括与一个或多个硫属元素组合的周期表第14族中的一个或多个元素。 一些实施例包括形成存储器单元的方法。