公开(公告)号：US12197550B2

公开(公告)日：2025-01-14

申请号：US17572762

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Diana C. Majerus ,  Brenda D. Kraus ,  Ying Zhang ,  Soo Koon Ng

IPC: G06F21/00 ,  G06F21/32 ,  G06V40/16

Abstract: Methods and devices associated with providing access to a computing device are described. A method can include generating a real-time image including an attempted user, comparing the real-time image to a reference image of an authorized user, identifying an obstructed portion of the attempted user, comparing an unobstructed portion of the attempted user to a portion of the authorized user corresponding to the unobstructed portion of the attempted user, providing access to a computing device in response to the unobstructed portion of the attempted user matching the portion of the authorized user, and rejecting access to the computing device in response to the unobstructed portion of the attempted user being different from the portion of the authorized user.

公开(公告)号：US12046658B2

公开(公告)日：2024-07-23

申请号：US16509204

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： An-Jen B. Cheng ,  Brenda D. Kraus ,  Sanket S. Kelkar ,  Matthew N. Rocklein ,  Christopher W. Petz ,  Richard Beeler ,  Dojun Kim

IPC: H01G4/018 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H10B12/00 ,  H01G4/005

CPC classification number: H01L29/517 ,  H01G4/018 ,  H01L21/02156 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/28194 ,  H10B12/30 ,  H01G4/005 ,  H01L21/02164 ,  H01L21/02194

Abstract: Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.

公开(公告)号：US20240136391A1

公开(公告)日：2024-04-25

申请号：US18047978

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Sanket S. Kelkar ,  Michael Mutch ,  Luca Fumagalli ,  Hisham Abdussamad Abbas ,  Brenda D. Kraus ,  Dojun Kim ,  Christopher W. Petz ,  Darwin Franseda Fan

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01G4/008 ,  H01G4/1218 ,  H01L27/10814 ,  H01L27/10852

Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.

公开(公告)号：US11467850B2

公开(公告)日：2022-10-11

申请号：US17094976

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Brenda D. Kraus ,  Yifen Liu

IPC: G06F9/44 ,  G06F9/4401 ,  G06N20/00 ,  G06F9/445

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

公开(公告)号：US10964532B2

公开(公告)日：2021-03-30

申请号：US15857920

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Sumeet C. Pandey ,  Brenda D. Kraus ,  Stefan Uhlenbrock ,  John A. Smythe ,  Timothy A. Quick

IPC: H01L21/02

Abstract: Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

公开(公告)号：US20230121315A1

公开(公告)日：2023-04-20

申请号：US18083428

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B41/27

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US11251261B2

公开(公告)日：2022-02-15

申请号：US16415487

申请日：2019-05-17

Applicant: Micron Technology, Inc.

Inventor： Sanket S Kelkar ,  An-Jen B. Cheng ,  Dojun Kim ,  Christopher W. Petz ,  Matthew N. Rocklein ,  Brenda D. Kraus

IPC: H01L27/108 ,  H01L21/768 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.

公开(公告)号：US20210358919A1

公开(公告)日：2021-11-18

申请号：US16874260

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Dojun Kim ,  Sanket S. Kelkar ,  Christopher W. Petz ,  Anthony J. Kanago ,  Brenda D. Kraus ,  Soichi Sugiura

IPC: H01L27/108 ,  H01L29/49 ,  H01L21/28 ,  C23C16/34 ,  C23C16/455 ,  C23C16/56 ,  C23C16/24

Abstract: Methods for forming microelectronic devices include forming a titanium nitride (TiN) material over a precursor structure. Forming the TiN material comprises repeating cycles of flowing a titanium-including gas adjacent the precursor structure; flowing a reducing gas over the precursor structure; flowing a nitrogen-including gas over the precursor structure; and, before and after flowing the nitrogen-including gas, purging gas. Related microelectronic device and related electronic systems are also described.

公开(公告)号：US20210005732A1

公开(公告)日：2021-01-07

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20150318369A1

公开(公告)日：2015-11-05

申请号：US14754211

申请日：2015-06-29

Applicant: Micron Technology, Inc.

Inventor： Brenda D. Kraus ,  Eugene P. Marsh

IPC: H01L29/423 ,  H01L21/285 ,  H01L21/28

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/28273 ,  H01L21/28556 ,  H01L29/7881 ,  Y10S438/964 ,  Y10S977/943

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.